3D NAND Z-Pitch Patents: Who Leads, Where the Gaps Are 2026
- Concentrated at the top. The top 5 assignees hold 54.5% of all 66 records in scope, and the top 10 hold 77.3% — a short list of firms controls most of the documented claim space.
- Filing has cooled since 2019. Activity peaked at 8 records in 2019 and the 2022 midpoint sits at 0, pointing to a lull rather than sustained growth into the most recent years (publication lag understates the latest year regardless).
- Manufacturing and device classes dominate. H10B (memory device manufacture) and H01L/H10D (semiconductor devices) carry the bulk of the class weight, alongside a surprising concentration in image/display classes worth checking before you file.
Top-5 share is the combined record count of the five largest assignees divided by all 66 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This dataset tracks patent activity around 3D NAND z-pitch and vertical scaling — the methods used to shrink layer pitch, manage high-aspect-ratio etch and patterning, and preserve memory window and retention as NAND strings stack higher. The scope spans 2015 through the 2026-07-31 cut-off and captures 66 published records across 27 ranked assignees.
The receiving-office split is led by the United States, with South Korea, China, WIPO/PCT, Japan and Europe each contributing a smaller slice — consistent with a technology where fabrication and equipment IP is filed close to where the wafers run.
Filing trend and technology composition
Two views of the same 66 records: when the filings happened, and which IPC subclasses carry the claim weight. Neither view should be read in isolation — a quiet recent year says more about publication lag than about interest.
A peak in 2019, then a lull
Filings rose from zero in 2017 to a peak of 8 in 2019, then fell back — the 2022 midpoint reads 0, and the curve stays flat toward the 2026 cut-off. Because publication trails filing by roughly 18 months, the last one or two years will always look thinner than they eventually turn out to be.
Manufacturing and device classes lead, with an image-processing overlap
H10B (memory device manufacture) and H01L (semiconductor devices) each cover 36.4% and 33.3% of the 66 records respectively, with H10D and H10P adding further device-level depth. The presence of H04N, G06T and G09G at 30%+ each signals that a meaningful share of these records intersect image/display signal-processing claims — worth checking case-by-case rather than assuming they are core NAND fabrication art.
Shares are the percentage of the 66 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on 3D NAND Z-Pitch and Vertical Scaling with Eureka
This page is one run against one query. Ask Eureka your own question about 3d nand z-pitch and vertical scaling and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited records and a representative filing
Film stack simplification for high aspect ratio patterning and vertical scaling
Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and…Abstract truncated as published; filed by Lam Research Corporation.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20160164738A1 | Vertical Scaling Of Computing Instances | 63 |
| 2 | US20120026368A1 | Binning compensation filtering techniques for image signal processing | 60 |
| 3 | US20070121380A1 | Location-specific NAND (LS NAND) memory technology and cells | 45 |
| 4 | CN101179671A | 图像缩放装置和图像缩放方法 | 27 |
| 5 | US6738072B1 | Graphics display system with anti-flutter filtering and vertical scaling feature | 27 |
| 6 | US5293432A | Document image scanner with variable resolution windows | 27 |
| 7 | US20120268655A1 | Graphics Display System with Anti-Flutter Filtering and Vertical Scaling Feature | 25 |
| 8 | US20060290708A1 | Graphics display system with anti-flutter filtering and vertical scaling feature | 21 |
| 9 | WO2020055837A1 | Film stack simplification for high aspect ratio patterning and vertical scaling | 17 |
| 10 | JP2002184874A | Semiconductor device | 17 |
Citation counts favour older filings simply because they have had more time to accumulate citations — treat this as a signal of influence within the searched corpus, not of current technical importance.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Three read-outs from the concentration, trend and class data that matter more than the raw counts on their own.
A short list controls most of the ground
With the top 5 assignees holding 54.5% of all 66 records and the top 10 holding 77.3%, this is not a fragmented field. A new entrant is filing directly into territory a small number of established players have already staked out.
The curve has cooled, not accelerated
Filing activity peaked at 8 records in 2019 and the 2022 midpoint sits at 0. That does not necessarily mean the technology is exhausted — publication lag of roughly 18 months means the most recent years understate real filing activity.
Manufacturing classes carry the weight
H10B (memory device manufacture) and H01L (semiconductor devices) each sit above a third of all 66 records, meaning process and structure claims are the densest part of the field — exactly where a new filer will hit the most prior art.
Co-filing is limited but pointed
Only 10 co-assignee pairs appear across the corpus, and the strongest repeated pairing centres on a single individual inventor-assignee working with two different co-assignees — a sign of a narrow, personal collaboration network rather than broad industry consortia.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to 3d nand z-pitch and vertical scaling, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| XIE XIAODONG | TANG CHENGFUH JEFFREY | 3 |
| XIE XIAODONG | PATTERSON JAMES T | 3 |
| XIE XIAODONG | MACINNIS ALEXANDER G | 3 |
| XIE XIAODONG | KRANAWETTER GREG A | 3 |
| TANG CHENGFUH JEFFREY | PATTERSON JAMES T | 3 |
| TANG CHENGFUH JEFFREY | MACINNIS ALEXANDER G | 3 |
| TANG CHENGFUH JEFFREY | KRANAWETTER GREG A | 3 |
| SIMSEK EGE FATMA A | KOVAL RANDY J | 3 |
With only 10 co-assignee pairs across 66 records, most filings in this space are solo efforts rather than joint ventures.
Who is filing, and who has room to move
The ranked leaders in this dataset span large semiconductor equipment and device makers alongside individual inventor-assignees, and the gap between the leader and the mid-table is wide.
The top assignee holds a clear lead
The leading assignee's 14 records is more than four times the fifth-place count of 3, marking a genuine gap at the top rather than a tight cluster of comparable filers.
The mid-table is flat
From roughly fifth place down through tenth place, counts hold steady at 3 records apiece — a wide plateau of similarly sized filers rather than a steep drop-off.
A long tail of small and single-filing entrants
Beyond the top 10, the ranking runs to 27 assignees in total, many holding a handful of records each — evidence of a field where individual inventors and smaller entities still stake claims alongside the majors.
| Assignee | Recent year | YoY |
|---|---|---|
| Broadcom Inc. | 0 | — |
| Lam Research Corporation | 0 | — |
| Intel Corporation | 0 | — |
| Microsoft Technology Licensing, LLC | 0 | — |
| Amazon Technologies, Inc. | 0 | — |
| XIE XIAODONG | 0 | — |
| THOMAS MAMMEN | 0 | — |
| TANG CHENGFUH JEFFREY | 0 | — |
Where to take this next
The dataset points to where filing pressure sits today and where it has eased — the next step is testing a specific claim against that ground.
Check a draft claim against the leaders' portfolios
Before filing into z-pitch or memory-hole scaling, run a candidate claim against the ranked leaders' existing filings to see how much of the core process space is already occupied.
Search assignee portfolios in EurekaTrack the momentum shift for early signals
Because publication lag understates the most recent one to two years, a fresh momentum check closer to filing time will show whether the 2019 peak is truly behind the field or about to repeat.
Set up a filing alert in EurekaCommon questions on 3D NAND z-pitch patents
The dataset ranks 27 assignees, with the leading company holding 14 of the 66 records in scope — more than four times the count held by the fifth-ranked filer at 3. The top 5 assignees together account for 54.5% of all 66 records, and the top 10 account for 77.3%, so a small group controls most of the documented claim space. Anyone entering this field should expect to file close to, or directly against, that group's existing coverage.
Not on the evidence of this filing trend: activity peaked at 8 records in 2019, and by the 2022 midpoint the count had dropped to 0. That points to a cooling rather than an accelerating field, though publication lag of roughly 18 months means the very latest years always look thinner than they eventually turn out to be once more filings publish. Treat any single recent year with caution rather than reading it as a trend on its own.
The heaviest classes are H10B (memory device manufacture) and H01L (semiconductor devices), each covering roughly a third of the 66 records, with H10D and H10P adding further device-level depth. A notable share of records also carry H04N, G06T and G09G classifications tied to image and display signal processing, which is worth checking case by case since it may reflect adjacent claim scope rather than core fabrication art. Because a single record can carry multiple classes, these shares add up to more than 100% and should not be summed.
Based on the class composition and the flat recent-year momentum across the leading assignees, sub-areas such as wordline resistance compensation, memory-window retention diagnostics under high-aspect-ratio etch, and string-stacking alignment tolerancing carry comparatively light documented density relative to core memory-hole and stacking claims. That does not guarantee freedom to operate — it means the searched corpus shows fewer claims specifically targeting those angles. Any claim drafted there should still be checked against the leading assignees' broader portfolios before relying on the gap.
US20220051938A1, filed by Lam Research Corporation and published 2022-02-17, covers methods for forming patterned multi-layer stacks that use a sacrificial silicon-containing non-metal material — such as silicon oxycarbide in place of silicon nitride — to maintain etch contrast while patterning a high-aspect-ratio stack, before that sacrificial material is selectively removed and replaced with metal. It is directly relevant to anyone using metal-replacement or gate-last approaches in high-aspect-ratio 3D NAND patterning. Reviewing its specific process sequence and material substitutions is the practical first step before designing a similar film-stack approach.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.