3D Stacked IC Thermal Management — Patent Landscape 2026
3D Stacked IC Thermal Management Patents
Vertical die integration in 3D stacked ICs dramatically elevates power density and creates vertically aligned hotspots that standard cooling cannot address. This dataset spans 2012–2026 patent and literature records across four distinct thermal solution clusters.
Why Thermal Management Defines 3D IC Design Limits
3D stacked IC technology integrates multiple semiconductor dies vertically through Through-Silicon Vias (TSVs), enabling higher bandwidth and reduced interconnect length. However, vertical compression introduces four compounding thermal challenges: elevated power density per unit footprint, vertically aligned hotspots causing localized temperature superposition across layers, thermomechanical stress from coefficient-of-thermal-expansion mismatches, and structural fragility of thinned dies under sub-100 µm thickness.
In this dataset, thermal management approaches cluster into four solution domains: integrated microfluidic and microchannel cooling, thermoelectric cooling (TEC), architectural and workload-aware software thermal control, and simulation and predictive modeling tools. Patents retrieved span US, CN, WO, and IN jurisdictions, with publication dates ranging from 2012 to August 2026.
The timeline divides into three phases. The Foundational Phase (2012–2015) established conceptual frameworks for power-and-thermal co-management in multi-die TSV stacks. The Development Phase (2018–2022) saw Micron Technology, Google, AMD, and Antoninus Thermal Management LLC file sustained series on microfluidic and thermoelectric approaches. The Recent Intensification Phase (2023–2026) shows the highest concentration of new filings, particularly from Chinese entities targeting liquid cooling architectures and AI-server thermal management.
Microfluidic cooling is the most heavily filed cluster in this dataset, with at least 10 distinct patents covering embedded microchannel architectures. Antoninus Thermal Management LLC holds the largest single-assignee filing volume in this dataset with approximately 7 records. The 2024–2026 CN filing surge is notable, driven by liquid cooling and AI-server thermal management applications across academic and commercial entities in retrieved records.
Filing Trends and Technology Cluster Distribution
Patent activity in this dataset spans four solution clusters across US and CN jurisdictions, with the most recent intensification visible in 2024–2026 filings. Microchannel cooling dominates by volume in retrieved records, while TEC and architectural management show sustained US-centric concentration.
Patent Records by Technology Cluster — 3D Stacked IC Thermal Management (Dataset Snapshot)
Integrated microchannel and microfluidic cooling accounts for the largest share of retrieved records in this dataset, with at least 10 distinct patents, followed by architectural/workload-aware management and thermoelectric cooling clusters.
↗ Click bars to exploreFiling Activity by Phase — 3D Stacked IC Thermal Management (Dataset Snapshot)
In this dataset, the 2024–2026 window shows the highest concentration of new filings, with a notable surge from Chinese entities in liquid cooling and AI-server thermal management relative to earlier phases.
↗ Click bars to exploreKey Application Areas in 3D Stacked IC Thermal Management
Retrieved records identify five primary application domains where 3D stacked IC thermal management solutions are actively deployed or targeted: HPC and AI accelerators, data centers and AI servers, 3D DRAM and processor-memory integration, chiplet and heterogeneous 2.5D/3D packaging, and manycore Network-on-Chip processors.
HPC and AI Accelerator Workloads
The most prominent application domain in this dataset. Shenzhen Yirei Technology Co., Ltd. (2026, CN) targets layered heat dissipation specifically for high-power modules including AI acceleration units. Tsinghua University (2025, CN) incorporates thermal management as a constraint in the AI chip design flow for compute-in-memory architectures based on 3D stacking. Thermal-aware 3D systolic ML accelerator design space exploration is treated in literature as an architectural optimization problem.
AI / HPCData Centers and AI Server Chips
Suzhou Huasheng Source Electromechanical Co., Ltd. (2025, CN) addresses multi-source thermal management for AI server chips using heat pipe arrays, distributed thermocouple arrays, and 3D coupled thermal models. Qualcomm Inc. (2026, CN) places distributed thermal sensors and controllers within CPU, GPU, neural signal processor, and always-on subsystem blocks of a SoC. Beijing Zhongke Xianluo Intelligent Computing Technology Co., Ltd. (2025, CN) addresses rack-level liquid cooling via cold-plate modules in a T3 architecture.
Data Center3D DRAM Processor-Memory Integration
Stacking DRAM above processor dies creates a thermal blanket effect. AMD’s integrated TEC (2019, US) sandwiches a thermoelectric cooler between the 3D DRAM stack and logic core layers, exploiting the temperature inversion where DRAM is cooler than the logic core. Google LLC’s TEC (2019, US) targets HBM components stacked adjacent to high-power ASICs with conductive pillar arrays. Literature on 3D die-stacked DRAM confirms that thermal-aware task allocation reduced energy consumption by 7.6% in one documented study.
Memory IntegrationChiplet and Heterogeneous 2.5D/3D Packaging
Qualcomm’s Single hybrid SoC die structure (2025, US/WO) explicitly includes a thermal mitigation stack of dummy semiconductor material as part of the HBM+SoC package architecture. Ningbo Biang-Xin Technology Co., Ltd. (2025, CN) performs multi-physics co-simulation of TSV and micro-bump vertical interconnects with 20–50 µm diameter, combining accuracy and computational speed for early-stage chiplet design. Peking University’s 2026 CN pending application addresses thermal non-uniformity introduced by DRAM memory stacking on logic cores in 3D-stacked architectures.
Chiplet / HeterogeneousLeading Assignees in 3D Stacked IC Thermal Management — Dataset Snapshot
In retrieved records, Antoninus Thermal Management LLC holds the largest single-assignee filing volume in this dataset with approximately 7 records concentrated in microchannel and predictive modeling approaches. US-based semiconductor majors — including Micron Technology, TSMC, IBM, and Intel — each hold between 3 and 4 records in this dataset, spanning TEC, architectural management, and simulation clusters.
Top Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreAntoninus Thermal Management LLC
Antoninus Thermal Management LLC holds approximately 7 records in this dataset, the largest single-assignee volume in retrieved records, spanning filings from 2022 provisional through multiple continuations to mid-2025. Key patents include chip-size double-layer and multi-layer microchannel (DLMC/MLMC) architectures demonstrating greater than 10°C peak temperature reduction, and a 2025 predictive thermal model using support vector regression (SVR) for design-time cooling strategy optimization. Filing status includes multiple active US continuations concentrated in the integrated chip-size microchannel and 3D IC thermal management space.
United StatesIntel Corporation
Intel holds approximately 3 records in this dataset across US and WO jurisdictions, with filings from 2022 to 2025. Key patents include a cross-die virtual sensing framework where victim dies ingest thermal telemetry from aggressor dies for IP domain-level performance management (2022/2025, US/WO), and a 2025 US patent on thermal performance in hybrid-bonded 3D die stacks addressing in-stack thermal material engineering. These represent active IP positions across both architectural management and structural bonding thermal solution clusters.
United StatesFive Emerging Directions in 3D IC Thermal Management (2024–2026)
Based on patent records with publication dates in 2024–2026 in this dataset, five directional signals are visible: AI-driven predictive thermal control, hybrid-bonded die stack thermal interface innovation, chiplet-aware co-design of thermal and electrical interconnects, intelligent thermal field reconstruction, and power-compute-thermal system co-optimization for data centers.
AI-Driven and Predictive Thermal Control
Machine learning integration is appearing explicitly in thermal management patents in retrieved records. Nanjing Jina Electronic Technology Co., Ltd. (2024, CN) applies ML and optimization algorithms for predictive heat flow simulation and path design. Antoninus LLC’s 2025 US patent incorporates support vector regression (SVR) for predictive cooling strategy optimization at design time. The Suzhou Huasheng Source heat pipe array system (2025, CN) constructs a 3D coupled thermal model before generating embedded cooling modules for AI server chips.
Hybrid-Bonded Die Stacks and In-Stack Thermal Material Engineering
Intel’s Thermal performance in hybrid bonded 3D die stacks (2025, US) addresses the thermal limitations of silicon-only bonded dies and the need for purpose-built thermal management dies within the stack. This represents a structural shift from post-packaging thermal solutions to in-stack thermal material engineering. Qualcomm’s hybrid SoC die structure (2025, US/WO) similarly includes a thermal mitigation stack of dummy semiconductor material as part of the HBM+SoC package architecture.
Microfluidic Cooling vs. Thermoelectric Cooling for 3D Stacked ICs
Click any row to explore further.
| Dimension | Microfluidic / Microchannel Cooling | Thermoelectric Cooling (TEC) |
|---|---|---|
| Patent volume in dataset | Largest cluster — at least 10 distinct patents in retrieved records | 4 distinct patents in retrieved records |
| Primary mechanism | Embedded micro-scale coolant channels (single-layer, DLMC, or MLMC) within or between stacked dies | Peltier effect heat pump targeting temperature-sensitive components (DRAM above logic cores) |
| Demonstrated performance | Greater than 10°C peak temperature reduction demonstrated (Antoninus LLC DLMC/MLMC, 2024) | Addresses asymmetric temperature inversion problem in processor-memory stacks; setpoint window control via feedback loop (TSMC, 2015) |
| Key assignees in dataset | Antoninus Thermal Management LLC, Shenzhen Mingruida, CETC 14th Research Institute, Shenzhen University, Yixin Micro Semiconductor | Google LLC, AMD, TSMC, GlobalFoundries |
| Jurisdiction concentration | US (Antoninus continuation portfolio) and CN (2024–2026 surge from Chinese entities) | Predominantly US filings; TSMC also filed CN; Google filed WO equivalent |
| Target application | High-power multi-layer stacks, AI servers, wafer-level packages, chip-size integration | HBM proximity cooling, 3D DRAM-logic stacks, 2.5D IC packages |
| Structural integration | Channels embedded within die stack; requires micro-pump infrastructure and coolant routing | TEC sandwiched between die layers or coupled to uppermost stack layer via conductive pillars |
| Adaptive control | Dynamic pump flow rates guided by thermal imaging or sensor feedback (Shenzhen Mingruida, 2025) | Temperature monitor feedback control loop maintaining internal temperature within defined setpoint (TSMC, 2015) |
Frequently Asked Questions: 3D Stacked IC Thermal Management Patents
Based on retrieved records, the four documented challenges are: (1) dramatically elevated power density per unit footprint, (2) vertically aligned hotspots causing localized temperature superposition across layers, (3) thermomechanical stress from coefficient-of-thermal-expansion mismatches between silicon, glass, and organic substrates, and (4) structural fragility of thinned dies (sub-100 µm) under thermal cycling.
In this dataset, Antoninus Thermal Management LLC holds the largest single-assignee filing volume with approximately 7 records. Their filings concentrate on chip-size integrated microchannel architectures (DLMC and MLMC) and predictive thermal modeling using support vector regression, spanning from a 2022 provisional through multiple US continuations to mid-2025.
The Antoninus Thermal Management LLC patent on optimization of thermal performance of 3D ICs utilizing chip-size double-layer or multi-layer microchannels (2024, US) demonstrated greater than 10°C peak temperature reduction through the DLMC and MLMC inter-layer cooling architecture.
Intel’s thermal management in horizontally or vertically stacked dies patent (2022, US — continued to 2025 and filed as WO) describes a cross-die telemetry framework where ‘victim’ dies ingest thermal data from ‘aggressor’ dies to estimate temperatures for IP domain-level performance management, without requiring physical sensors in every domain.
AMD’s integrated thermoelectric cooler for three-dimensional stacked DRAM and temperature-inverted cores (2019, US) addresses the temperature inversion problem in processor-memory stacks, where the DRAM layer is cooler than the underlying logic core. The TEC is sandwiched between the 3D DRAM stack and logic core layers to pump heat toward the warmer core layer.
Based on retrieved records, the 2024–2026 CN filing surge is predominantly in liquid cooling architectures and AI-server thermal management. Chinese entities filing in this period include academic institutions (Tsinghua University, Peking University, Beihang University, Nanjing University of Posts and Telecommunications) and commercial entities (Shenzhen Yiguang Era Technology, Yixin Micro Semiconductor Technology, Ningbo Biang-Xin Technology). These are largely CN-jurisdiction only filings, representing potential prior art but limited extraterritorial blocking risk according to the strategic analysis in retrieved records.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.