Backside Power Delivery Patents: Top Companies & Filing Trends 2026
Filing growth compares 2021 (14 records) with 2024 (29) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 143 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Backside power delivery moves the power rail off the front-side interconnect stack and onto the wafer backside, freeing signal routing tracks and shrinking cell height — a structural change that packaging and heterogeneous-integration teams now have to claim around rather than design past. This landscape tracks 143 published records filed between 2015 and mid-2026 that combine backside power-rail or buried power-rail claims with semiconductor packaging or heterogeneous-integration language, capturing the point where transistor-level backside routing meets die-level and package-level integration.
Because a single record often carries several IPC classes, the technology composition figures below are read against the full 143-record base, not against each other — they show where claim density sits, not a strict market split. Patent families, rather than raw document counts, are the more defensible unit here, since aggressive continuation filing and multi-jurisdiction re-filing can otherwise inflate a single invention into several records.
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Filing trend and technology composition
Two views of the same 143-record base: how filing activity has moved year over year, and which IPC subclasses carry the claim density once a record is tagged into more than one class.
Filing trend, 2017–2026
Filings ran near zero through 2017-2019, then climbed to a peak of 34 records in 2025. The 2021-to-2024 span is the cleanest read of real momentum — 14 records to 29, +107% — because 2025 and 2026 are still filling in behind an 18-month publication lag and should not be read as a plateau or a decline.
IPC subclass composition
H01L (semiconductor devices) appears on 83.2% of the 143 records, confirming that most backside power-delivery claims are still framed as general device architecture. H10W (33.6%), H10B memory device manufacture (25.2%) and H10D (22.4%) show where the more specific structural and memory-integration claims sit, while H10P, H01J, G02B and H05K each cover single-digit shares — narrow, less-contested corners of the same field.
Shares are the percentage of the 143 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Advanced Packaging & Heterogeneous Integration — Backside Power-Delivery Integration Patent Landscape with Eureka
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Try EurekaRepresentative and most-cited filings
Pillar-based MRAM embedded within a buried power rail, backside power distribution network
An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.Filed by IBM, published 2024 — one of the filings that ties memory-device integration directly to the buried power rail rather than treating the rail as a purely interconnect structure.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20200135718A1 | Architecture for monolithic 3D integration of semiconductor devices | 45 |
| 2 | US20200381430A1 | Compact 3D stacked-CFET architecture for complex logic cells | 27 |
| 3 | US20180182699A1 | Post-grind die backside power delivery | 20 |
| 4 | US20240128146A1 | Semiconductor package for enhanced cooling | 13 |
| 5 | US20240128150A1 | Semiconductor package structure for enhanced cooling | 13 |
| 6 | US10032707B2 | Post-grind die backside power delivery | 12 |
| 7 | US20230078381A1 | Tapered device for lateral gate all around devices | 10 |
| 8 | US20220416048A1 | Semiconductor structure having stacked gates and method of manufacture thereof | 9 |
| 9 | WO2023049132A1 | A 3D semiconductor device and structure with heat spreader | 7 |
| 10 | US20240071941A1 | Semiconductor packages and methods of manufacturing thereof | 7 |
Citation counts favour older filings simply because they have had more time to accumulate citations inside this corpus — treat them as a signal of influence on the field, not a ranking of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
The concentration and trend data point to a field where the core architecture is already claimed by a small group, but several adjacent structural questions remain open.
The core architecture is not open ground
Five assignees hold 92 of the 143 records in scope. New entrants filing on the base backside-power-rail structure are filing into space already dense with prior art from the largest holders; differentiation has to come from a specific structural or process detail, not the general architecture.
Real growth, not a recent spike
The three-year run from 14 records in 2021 to 29 in 2024 is the most reliable growth read in the dataset because it predates the publication lag that makes 2025 and 2026 look flat. Filing volume roughly doubled inside three years, consistent with backside power delivery moving from research demonstration toward production-relevant packaging claims.
Structural subclasses trail the general one
H01L captures the bulk of records because it is the default semiconductor-device classification, but H10W, H10B and H10D — the subclasses that map more specifically onto buried-rail and backside-via structures — sit at meaningfully lower shares. That gap is where more specific, harder-to-invalidate claims are still being written.
Filing activity is heavily US-anchored
The United States receives the large majority of filings, with Europe, WIPO/PCT and the United Kingdom each taking a much smaller share and China and India in single digits. A filing strategy built only around US coverage will miss most of the field's counterpart activity elsewhere, but it will also match where the bulk of enforceable rights currently sit.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to advanced packaging & heterogeneous integration — backside power-delivery integration patent landscape, with the prior art for and against each one.
Where to take this
The concentration at the top and the gaps in structural sub-classification both point to the same next step: a closer read of claim scope before committing a filing strategy.
Map claim scope against the leader's portfolio
With 64.3% of records held by five assignees, any new filing on core backside-rail architecture needs a freedom-to-operate check against the leader's claims specifically, not just a general prior-art search.
Explore assignee claims in EurekaTrack the structural sub-classes, not just the headline trend
H10W, H10B and H10D carry the more specific structural claims and sit well below H01L in density — worth monitoring as the field matures beyond general device architecture.
Set up a class-level alert in EurekaWatch for the 2025–2026 lag to resolve
The apparent flattening after 2024 is a publication-lag artefact, not a slowdown; re-check the trend once later filings finish publishing.
Run a fresh trend pull in EurekaFrequently asked questions
One assignee leads with 37 of the 143 records in scope, well ahead of the rest of the ranked field. The top five assignees combined hold 92 records, or 64.3% of all records in scope, and the top ten hold 88.1%. This is a concentrated landscape: a small number of companies control most of the claim space around backside power-rail and backside power-network architecture.
Yes, based on the most recent complete data: filings grew from 14 records in 2021 to 29 in 2024, a +107% increase over three years. 2025 shows 34 records as the current peak, but because publication typically lags filing by around 18 months, the 2025 and 2026 figures are still incomplete and should not be read as the trend flattening or reversing.
US20240090235A1, filed by IBM and published in 2024, claims an apparatus combining a backside power distribution network, a backside power rail joined to that network, and a backside contact via coupling a front-end-of-line transistor to the rail — where the contact via itself comprises a pillar-based memory device. In practical terms, it ties MRAM-style pillar memory integration directly to the buried power rail structure, rather than treating the rail purely as a power-interconnect feature. Anyone integrating memory elements into a backside power distribution network needs to check their via and contact geometry against this claim specifically.
The general device classification H01L covers 83.2% of the 143 records, but the more structurally specific subclasses — H10W at 33.6%, H10B (memory device manufacture) at 25.2%, and H10D at 22.4% — sit at meaningfully lower shares. That gap suggests claim space in specific backside via geometries, package-level redistribution layers, and thermal management for backside power networks is less densely occupied than the core architecture itself, even though the overall field looks crowded at the top.
The United States dominates with 100 of the 143 records in scope, far ahead of Europe (EPO) at 16, WIPO/PCT filings at 15, the United Kingdom at 5, and China and India at 2 each. A filing or freedom-to-operate strategy focused only on the US will capture most of the field's activity and enforceable rights, but it will miss counterpart filings in the other offices, particularly PCT applications that may still enter national phase elsewhere.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.