Chiplet Die-to-Die Interconnect Patents: Who Leads, Trends 2026
Filing growth compares 2021 (65 records) with 2024 (65) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 689 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This landscape tracks patent activity where chiplet interconnect, die-to-die and related bonding or fan-out packaging language intersects with semiconductor packaging and heterogeneous integration claims. It spans 689 published records filed or published between 2015 and mid-2026, drawn from a search built around D2D interconnect terminology paired with packaging and integration context rather than either concept alone.
The scope favours records that tie interconnect structure to a packaging or integration claim, which is why the IPC composition below is dominated by device-level classes (H01L, H10W) rather than pure protocol or software classes. Readers using this to plan freedom-to-operate work should treat the 689-record set as the denominator for every share quoted on this page.
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Filing trend and technology composition
Two views of the same 689-record set: the annual filing trend, and the IPC subclasses that carry the underlying technical claims.
Filing trend, 2017-2026
Filings rose from 19 in 2017 to a peak of 163 in 2025, with 2021-2024 essentially flat (65 to 65, 0% change). 2026 shows only 13 so far, but that reflects the roughly 18-month publication lag rather than a real drop in filing activity — the most recent one to two years always understate true volume.
IPC subclass composition
H01L (semiconductor devices) appears in 67.3% of the 689 records, and H10W in 36.9%, making these the two load-bearing classes. G06F (16.1%), H10B (14.8%), H10P (8.3%), H10D (7.0%), G11C (6.5%) and H05K (4.4%) each cover a meaningfully smaller slice, and because records can carry multiple classes these figures sum to well over 100%.
Shares are the percentage of the 689 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Advanced Packaging & Heterogeneous Integration — Chiplet Die-to-Die Interconnect Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about advanced packaging & heterogeneous integration — chiplet die-to-die interconnect patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited records in the field
On-package die-to-die (D2D) interconnect for memory using UCIe PHY
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.Filed by Intel Corporation, published 2024-09-19 as US20240311330A1 — one of the more recent filings to explicitly claim UCIe-aligned PHY structure for memory die-to-die links.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20140134803A1 | Method And System For A Semiconductor Device Package With A Die-To-Die First Bond | 272 |
| 2 | US20190244933A1 | 3D semiconductor device and structure | 159 |
| 3 | US20230207474A1 | Bonded structures with interconnect assemblies | 157 |
| 4 | US20160300817A1 | Semiconductor Device and Method of Forming a Package In-Fan Out Package | 128 |
| 5 | US20100283085A1 | Massively Parallel Interconnect Fabric for Complex Semiconductor Devices | 106 |
| 6 | US20140332966A1 | Epoxy-amine underfill materials for semiconductor packages | 91 |
| 7 | US6919508B2 | Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing | 87 |
| 8 | US20140134804A1 | Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond | 86 |
| 9 | US20140252655A1 | Fan-out and heterogeneous packaging of electronic components | 81 |
| 10 | US20060108678A1 | Probe arrays and method for making | 78 |
Citation counts favour older filings simply because they have had more time to accumulate citations inside this corpus — read them as a signal of influence on later filers, not as a ranking of current technical importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three read-throughs from the trend, class and concentration figures above, aimed at where to file and where not to.
Claim space at the top is already crowded
With the five leading assignees holding 47.8% of all 689 records and the top ten holding 60.5%, new entrants filing core die-to-die bonding or interconnect structure claims are filing into dense prior art held by a small number of large semiconductor and packaging firms.
Volume has plateaued, not declined
Annual filings were flat across 2021-2024. Because publication lags filing by around 18 months, the lower counts shown for 2025-2026 are an artefact of that lag and should not be read as slowing interest.
H10W is a large second class behind H01L
H01L covers 67.3% of records as expected for device-level packaging claims, but H10W's 36.9% share signals that a substantial share of filings frame the interconnect specifically around this newer heterogeneous-integration-adjacent classification rather than legacy device claims alone.
Older foundational filings still anchor the field
The most-cited record in the set dates to a 2014-published application on die-to-die first bonding, cited 272 times; high citation counts here mark documents that later filers had to design around, not necessarily the most commercially active claims today.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to advanced packaging & heterogeneous integration — chiplet die-to-die interconnect patent landscape, with the prior art for and against each one.
Where to take this next
The figures above establish where filing activity sits today. Turning that into a filing or freedom-to-operate decision needs a closer read of specific claims and adjacent white space.
Map claims against the leading assignees' portfolios
Concentration at the top means a new filing in core D2D bonding or interconnect structure likely overlaps prior claims from the leading assignees — worth a targeted claim chart before drafting.
Explore assignee portfolios in EurekaCheck the under-claimed sub-areas directly
Thermal management, test/validation and board-level assembly claims sit at lower filing density than the core H01L/H10W classes — a faster path to defensible claims than the crowded core.
Run a white space search in EurekaTrack momentum past the publication lag
Recent-year declines shown here are largely a publication-lag artefact; re-run the trend in 6-12 months once 2025-2026 filings finish publishing to see the real trajectory.
Set up a filing alert in EurekaCommon questions on this landscape
One assignee leads clearly with 100 records in this 689-record dataset, well ahead of the fifth-ranked company at 25 and the tenth at 11. That gap indicates one or two firms treat die-to-die interconnect as a core patent programme rather than an incidental filing area. The ranking covers the 100 companies the data endpoint returns, so it should be read as relative standing within that set, not as a share of every filer worldwide.
Filings were essentially flat from 2021 to 2024, holding at 65 in both years for 0% change. The 2025 peak of 163 and the lower 2026 count both need context: publication lags actual filing by roughly 18 months, so the most recent one to two years in any patent trend understate real activity. Treat the 2021-2024 window as the most reliable read on recent momentum.
H01L (semiconductor devices) appears in 67.3% of the 689 records and H10W in 36.9%, making these the two dominant classes by a wide margin. G06F, H10B, H10P, H10D, G11C and H05K each cover smaller but non-trivial shares, from 16.1% down to 4.4%. Because a single record can carry multiple IPC codes, these percentages add up to well over 100% and should not be summed into a single total.
US20240311330A1, filed by Intel Corporation and published 2024-09-19, covers on-package die-to-die interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer. It sits among the more recent filings in this dataset to explicitly tie a D2D structure to the UCIe standard rather than a proprietary interconnect scheme. Anyone building memory-chiplet links against UCIe PHY should read its specific claim language rather than relying on the abstract alone.
The composition data points to a few thinner branches relative to the dominant H01L and H10W core: thermal management at bonded D2D interfaces, known-good-die test and validation methods, H05K-class board-level chiplet assembly, and signal integrity claims at fine bond pitch. These areas show lower filing density in this dataset, which typically means less occupied claim space rather than lower commercial relevance. Any filing strategy there should still be checked against the leading assignees' broader portfolios before drafting.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.