Advanced Semiconductor Packaging Patents: Top Companies & Trends 2026
- Filing has already peaked. 2022 was the high-water mark at 152 families, and the count has not returned to that level since — this is a claim space that filled up, not one still accelerating.
- China now files more than the US and Taiwan combined. 611 China filings against 348 US and 121 Taiwan shows where examiners are building the deepest prior-art record for this technology.
- Even the biggest names went to zero last year. Assignees including major OSATs and foundries show 0 filings and -100% YoY in the latest year, though publication lag means recent filings are still working through the pipeline.
Filing growth compares 2021 (145 records) with 2024 (143) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,307 records in scope (CR5), not by the ranked leaders only.
What this patent set covers
This landscape covers 1,307 patent families filed against a search built around semiconductor packaging, advanced packaging and chiplet interconnect, cross-referenced against through-silicon via, underfill, warpage, redistribution layer and thermal interface terminology, and confined to H01L23, H01L21 and H01L25. That combination captures the structural and process claims that hold a die, its interconnect and its package body together, rather than the transistor design inside the die itself.
The record set runs from 2015 through the 2026 data cut-off, with the most recent year necessarily incomplete because publication typically lags filing by around eighteen months. Reading the trend line means treating the last one to two years as a floor, not a ceiling.
Filing trend and technology composition
The two views below show when this field was built out and which adjacent IPC subclasses the same applicants are also claiming into.
A field that peaked in 2022
Filings rose from 55 in 2017 to a peak of 152 in 2022, then declined — the midpoint year matching the peak signals a plateau rather than continued growth. Treat the tail end of the chart as understated rather than as a genuine downturn, given the publication lag, but the shape through 2022–2024 is a real signal that the core claim space is well occupied.
Concentrated in H01L, spilling into related subclasses
H01L covers all but three of the 1,307 records, confirming the search is on-target. The meaningful signal is in the smaller subclasses: H10W and H10P appear at scale (657 and 117 records respectively), and H05K, H10B, G03F, H01Q and H10D each carry a modest but non-trivial share — pointing to printed-circuit assembly, memory manufacture, lithography and antenna integration as adjacent claim territory rather than core territory.
Shares are the percentage of the 1,307 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Advanced Semiconductor Packaging and Interconnect with Eureka
This page is one run against one query. Ask Eureka your own question about advanced semiconductor packaging and interconnect and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art in this space
US11515269B2 — Semiconductor packaging structure having antenna module
A semiconductor packaging structure includes: a substrate, a redistribution layer having one conductive plugs, metal bumps disposed on the redistribution layer, and electrically connected with the redistribution layer including the conductive plug; a semiconductor chip over the redistribution layer and aligned to and electrically connected with the conductive plug; an underfill layer filling a gap between the redistribution layer and the semiconductor chip and the conductive plugs; a polymer layer on the redistribution layer, over the plurality of metal bumps, the underfill layer and the semiconductor chip, exposing only top parts of the plurality of metal bumps and top part of the semiconductor chip.Filed by SJ Semiconductor (Jiangyin) Corporation, published 2022-11-29 — abstract shortened for length.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6380048B1 | Die paddle enhancement for exposed pad in semiconductor packaging | 231 |
| 2 | US6867499B1 | Semiconductor packaging | 166 |
| 3 | US20100013081A1 | Packaging structural member | 133 |
| 4 | CN102324418A | 半导体元件封装结构与其制造方法 | 123 |
| 5 | US7023089B1 | Low temperature packaging apparatus and method | 118 |
| 6 | US20110050334A1 | Integrated Voltage Regulator with Embedded Passive Device(s) | 109 |
| 7 | US20090065907A1 | Semiconductor packaging process using through silicon vias | 109 |
| 8 | TW201023277A | Packaging structural member | 96 |
| 9 | US6774499B1 | Non-leaded semiconductor package and method of fabricating the same | 75 |
| 10 | US20140091455A1 | Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging | 70 |
Citation counts inside a searched corpus favour older filings simply because they have had more time to accumulate citations — read this as a map of foundational influence, not of current competitive priority.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns stand out once the raw counts are read against filing dates and jurisdictions.
The core claim space is already dense
Filings climbed for five years before topping out at 152 in 2022 and have not exceeded that since. A new entrant claiming the same redistribution-layer-plus-underfill combination is filing into prior art built up over roughly a decade, not into open ground.
China is the primary examination venue now
China's receiving-office count of 611 outweighs the United States (348) and Taiwan (121) combined, meaning freedom-to-operate searches limited to US and EPO prior art will miss the majority of the record for this technology.
Adjacent subclasses carry real volume
H10W alone accounts for 657 records against the 1,304 in core H01L, and H10P adds a further 117 — packaging claims are increasingly being written to also cover the wafer-level and power-device subclasses rather than staying inside H01L.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to advanced semiconductor packaging and interconnect, with the prior art for and against each one.
Who is active, and who has pulled back
Momentum data shows a field where several of the largest historical filers, including major OSATs and foundries, register zero output in the latest year — consistent with the overall peak-and-plateau trend rather than a sign any single company has exited the technology.
Latest-year counts should not be read as retreat
Assignees spanning OSATs, foundries and memory makers all show 0 filings in the latest year. Given the roughly 18-month publication lag, this is far more likely to reflect filings still in the pipeline than an actual pullback in R&D investment.
Foundry-to-design-house pairing stands out
Only nine co-assignee pairs appear across the dataset, and one pairing between a major foundry and a design-service partner accounts for 14 joint filings — an order of magnitude ahead of the next pairs, which sit at a single joint filing each.
Filing strategy is genuinely multi-jurisdictional
Beyond China and the US, Taiwan, WIPO/PCT, EPO and Japan all carry meaningful filing volume, indicating applicants in this space are routinely pursuing multi-region protection rather than filing domestically only.
| Assignee | Recent year | YoY |
|---|---|---|
| Advanced Semiconductor Engineering (ASE) | 0 | -100% |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | -100% |
| Shanghai Yibu Semiconductor Co., Ltd. | 0 | -100% |
| Applied Materials, Inc. | 0 | — |
| ChangXin Memory Technologies, Inc. | 0 | — |
| Powertech Technology Inc. | 0 | — |
| Intel Corporation | 0 | — |
| Siliconware Precision Industries Co., Ltd. (SPIL) | 0 | — |
Where to take this next
The dataset points to specific follow-up work depending on whether the goal is freedom-to-operate, white space discovery or competitive tracking.
Run a China-inclusive FTO search
With 611 of 1,307 families filed through China's receiving office, any clearance search that stops at US and EPO prior art is working from less than a third of the relevant record.
Explore Eureka's global search →Map the adjacent IPC subclasses in detail
H10W and H10P volumes suggest packaging claims are increasingly written to reach into wafer-level and power-device territory — worth a dedicated pass rather than treating H01L as the whole picture.
Open Eureka's IPC breakdown →Track the foundry-design house pairing
The strongest co-assignee pair in this dataset files at more than ten times the rate of any other pair, making it a useful bellwether for where joint packaging-and-design filings are headed next.
Watch assignee activity in Eureka →Common questions about this landscape
The assignee ranking behind this landscape is dominated by a mix of Taiwanese OSATs and foundries, memory manufacturers and equipment suppliers, several of which appear repeatedly across both the citation table and the momentum data. Rather than a single dominant holder, the field shows concentration among a handful of large East Asian manufacturers with a long tail of smaller filers. Because publication lags filing, the most recent year understates activity for all of them, so current rankings should be treated as directional rather than final.
No — filings rose from 55 in 2017 to a peak of 152 in 2022 and have not returned to that level since, which is a plateau-and-decline pattern rather than continued growth. Some of the apparent drop in the most recent one to two years is an artefact of the roughly 18-month gap between filing and publication, so the true 2024-2025 numbers are likely higher than currently shown. Even accounting for that lag, the shape of the curve through its peak year is a genuine signal that the core claim space filled up rather than kept expanding.
China leads with 611 filings through its receiving office, ahead of the United States at 348 and Taiwan at 121, with WIPO/PCT, the EPO and Japan each contributing smaller but non-trivial volumes. This means a prior-art or freedom-to-operate review limited to US and European filings will miss the majority of the documented activity in this technology. Applicants are also clearly pursuing multi-jurisdiction protection given the spread across six distinct receiving offices rather than concentrating in one home market.
US11515269B2, assigned to SJ Semiconductor (Jiangyin) Corporation and published in November 2022, claims a semiconductor packaging structure combining a redistribution layer with conductive plugs, metal bumps electrically connected to that layer, a semiconductor chip aligned to the plugs, an underfill layer filling the gap beneath the chip, and a polymer layer that exposes only the top of the bumps and chip. It is representative of the structural approach much of this dataset takes: building the interconnect stack around a redistribution layer rather than through-silicon vias alone. Anyone designing an antenna-integrated or fine-pitch RDL package should review this claim scope specifically rather than assuming it only covers antenna modules.
The smaller IPC subclasses in this dataset — printed-circuit assembly (H05K), memory device manufacture (H10B), photolithography (G03F), antennas (H01Q) and general semiconductor devices (H10D) — carry meaningfully lower filing volume than the core H01L and H10W territory, suggesting thinner prior art at those intersections. Specific sub-areas worth checking include thermal interface materials for stacked die, warpage control in fan-out packaging and chiplet-to-chiplet interconnect bonding, none of which show the density seen in core redistribution-layer claims. A thin subclass is not proof of open ground, but it is a reasonable place to start a deeper freedom-to-operate check before committing to a filing strategy there.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.