The ranked leader holds 717 records out of 41,171 in scope, with fifth place at 447 and tenth at 291. The field is fragmented rather than dominated: the top 5 assignees combined account for only 7.3% of all records, and the top 10 for 11.4%. That means freedom-to-operate risk is spread across many mid-sized portfolios rather than concentrated in one or two blocking players.

No. Filings rose from 755 in 2017 to a peak of 855 in 2022, and have declined since. Several of the most active historical assignees show sharp year-on-year drops in the most recent year, some down as much as 90% or more. Because publication lags filing by around 18 months, the very latest year is always undercounted, but the multi-year direction is clearly downward from the 2022 peak, not upward.

Coding and code conversion (IPC class H03M) is the densest area by a wide margin, covering 16.6% of all 41,171 records. The next largest classes — transmission (H04B) and digital data processing (G06F) — sit at 5.1% and 4.1% respectively. Since a single record can carry multiple IPC classes, these percentages are not mutually exclusive shares of a whole; they show where claim density concentrates, not a strict partition of the field.

Sub-areas adjacent to the dense coding and transmission clusters carry noticeably fewer records, including IR-drop compensation calibration loops, mixed-signal bit-slicing for multi-bit weights, and runtime tracking of achievable effective bit precision. These sit inside the same broad application area covered by the search terms but are not where the bulk of the 41,171 records concentrate. Anyone drafting new claims should check density in these specific sub-areas before assuming the ground is occupied, since aggregate filing volume in the field overall does not mean every technical branch is equally claimed.

US20240396568A1, filed by Intel and published in November 2024, describes a compute-in-memory pipeline: a DAC stage converts digital activations to analog signals, a multiply-accumulate stage combines them with stored multi-bit weight data, an analog integration stage performs partial sum accumulation, and an ADC stage converts the final result back to digital. The claim scope centres on keeping accumulation in the analog domain across multiple multiply-accumulate operations before a single final conversion step, rather than converting after each operation. Anyone designing a similar pipeline should check where their own accumulation happens relative to the ADC stage.