Atomic Layer Etching HARC Technology Landscape 2026
Atomic Layer Etching for High Aspect Ratio Contacts
ALE has evolved from a research curiosity to a production-enabling technology for HARC structures. Samsung’s reversed HARC patents and Lam Research’s bottom-up fill work signal ALE is now embedded in leading-edge logic roadmaps at 2 nm and below.
ALE Mechanisms and HARC Integration Context
Atomic Layer Etching removes material with atomic-scale precision using sequential, self-limiting surface reactions. Within this dataset, ALE activity spans three mechanistic regimes: plasma-enhanced anisotropic ALE, thermal isotropic ALE, and wet-chemical ALE — all applied to high aspect ratio contact formation where conventional plasma etch causes sidewall damage and poor depth uniformity.
Plasma-enhanced ALE separates the etch cycle into a surface-modification step — such as chlorine adsorption — and an energetic ion-driven desorption step, enabling directional, monolayer-by-monolayer removal. This is the dominant approach for anisotropic HARC formation in silicon, GaN, and compound semiconductors, preventing microloading and aspect-ratio-dependent etch rate variation that degrades deep contacts.
Thermal ALE uses sequential thermally driven chemical reactions — conceptually the reverse of atomic layer deposition — achieving isotropic, damage-free removal with sub-angstrom control applicable to gate dielectrics and ultra-thin channels below 10 nm. Wet-chemical ALE uses oxidant/etchant cycling in liquid phase, as demonstrated for Ge/GeSi nanowire formation targeting vertical gate-all-around FETs.
In this dataset, the innovation is concentrated in a small number of large-cap players — Samsung, Lam Research, GlobalFoundries, TSMC, and Synopsys — with specialty chemical companies such as Kanto Denka Kogyo also filing process chemistry IP. The earliest HARC-relevant patent in retrieved records dates to 1997 (Micron Technology), spanning nearly three decades of documented integration challenges.
ALE Technology Clusters and Filing Timeline in This Dataset
Four distinct technology clusters emerge from the retrieved records: plasma-enhanced directional ALE, thermal/isotropic ALE, ALE-enabled bottom-up fill, and advanced HARC structural architectures. Filing activity spans 1997 to 2024 with the most structurally novel filings concentrated in 2022–2024.
ALE-HARC Patent Records by Technology Cluster (Dataset Snapshot)
In this dataset, advanced HARC structural architectures and plasma-enhanced directional ALE account for the largest share of patent records, with Samsung and GlobalFoundries as the primary contributors to these two clusters respectively.
↗ Click bars to exploreALE-HARC Filing Activity by Era in Retrieved Records
In this dataset, the 2020–2024 period produced the highest concentration of structurally novel HARC filings, including Samsung’s reversed HARC patents and Synopsys’ CFET self-limiting etch, reflecting the acceleration of 3D logic architecture demands.
↗ Click bars to exploreKey Application Domains for ALE in HARC Contact Formation
ALE addresses HARC contact challenges across four primary semiconductor domains in this dataset: advanced logic at sub-5 nm nodes, GaN power semiconductors, 3D NAND memory metallization, and self-aligned contact formation for DRAM and logic.
Sub-5 nm Logic and GAA/CFET
Samsung’s 2023 reversed HARC patents (US and EP) claim a via that penetrates through ILD, STI, and bulk silicon to connect a front-side contact to a backside power rail — the defining structural challenge at the 2 nm node and beyond. Synopsys’ 2024 CFET patent introduces a blocking material and self-limiting etch sequence to prevent n/p contact shorting in vertically stacked complementary FETs. The directional silicon ALE literature (2015) explicitly targets single-digit nm gate lengths and half-pitches.
Advanced LogicGaN Power Semiconductor Gate Recess
A 2023 study on normally-off GaN MIS-HEMTs using ALE demonstrates a recessed AlGaN gate with 3.7 nm remaining barrier layer, Ra = 0.40 nm surface roughness, 608 mA/mm drain current, and threshold voltage of +2.0 V — competitive breakdown performance without surface damage. A 2022 study on InAlN/GaN heterostructures achieves an etch per cycle of 0.15 nm/cycle with RMS roughness of 0.61 nm, superior to all continuous etch alternatives evaluated.
Power Semiconductors3D NAND and Memory Contact Fill
GlobalFoundries’ 2014 patent addresses MOL/BEOL contacts at aspect ratios greater than 6:1 and often exceeding 10:1, identifying void and seam formation as the dominant yield failure mode in conventionally plated HARC contacts. Lam Research’s 2017 patent explicitly claims ALE use to condition contacts and vias for bottom-up fill via electroless deposition of cobalt — directly applicable to wordline and contact hole fill in 3D NAND stacks where aspect ratios routinely exceed 50:1 at current production generations.
Memory MetallizationSelf-Aligned Contact for DRAM and Logic
TSMC’s 2001 patent addresses self-aligned contact landing accuracy using spacers on ILD layer sidewalls, a technique foundational to yield-limited HARC SAC processes. GlobalFoundries’ 2015 GCIB patent introduces a gas cluster ion beam process to deposit a horizontally formed etch stop layer within a narrow HARC opening — a directional deposition approach complementary to ALE trimming for self-aligned contact landing accuracy at advanced nodes.
SAC FormationKey Patent Assignees in ALE HARC Technology (Retrieved Records)
In this dataset, filing activity is concentrated among a small number of named assignees. Samsung Electronics holds the most structurally advanced HARC architecture patents in retrieved records, filing the reversed HARC structure in both US and EP jurisdictions in 2023, while Lam Research is the only major etch equipment OEM directly represented in this dataset on the ALE fill and integration topic.
Top Assignees by HARC-Relevant Patent Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreSamsung Electronics
Samsung holds 4 HARC-relevant patent records in this dataset, including the reversed HARC structure and process filed in both US (2023) and EP (2023) jurisdictions — representing the most structurally advanced HARC geometry targeting backside power delivery. The reversed HARC patent claims a via that penetrates through ILD, STI, and the wafer to connect a front-side contact to a backside power rail, directly addressing 2 nm node and beyond integration requirements. Both filings represent cross-jurisdictional protection for this architecture, establishing a foundational IP position in this dataset.
South Korea / US, EPLam Research Corporation
Lam Research is the only major etch equipment OEM directly represented in this dataset on the ALE fill and integration topic, with a 2017 US patent explicitly claiming ALE use to condition contacts and vias for bottom-up fill via electroless deposition of cobalt. This patent is the first major equipment vendor filing in retrieved records linking ALE to HARC fill yield improvement, positioning ALE as a pre-fill surface conditioning step. The patent covers HARC contacts and vias applicable to both logic and memory device generations.
United StatesFrontier Trends in ALE HARC Technology (2022–2024)
The most recent filings and publications in this dataset (2022–2024) reveal five emerging directions: reversed HARC for backside power delivery, CFET self-limiting etch for vertical channel contacts, new acid halide ALE chemistries, GaN power device gate recess maturation, and ALD/ALE integration for HARC reliability.
Reversed HARC for Backside Power Delivery (2023)
Samsung’s reversed HARC patents filed in 2022/2023 claim the most geometrically demanding HARC structure documented in this dataset: a via that penetrates the full wafer from front-side MOL contact down to a backside power rail, passing through ILD, STI, and bulk silicon. This architecture requires ALE-class etch depth control at aspect ratios that dwarf conventional HARC contacts. Both US and EP counterparts are filed, establishing cross-jurisdictional protection.
CFET Self-Limiting Etch Migrating into EDA (2024)
Synopsys’ 2024 CFET patent introduces a blocking material and self-limiting etch sequence to prevent n/p contact shorting in vertically stacked complementary FETs. This represents ALE-inspired design methodology being embedded into design rule checking and process simulation tools — a signal that ALE process concepts are migrating from fab-floor process IP toward design-technology co-optimization (DTCO). IP strategists should monitor EDA vendors for further DTCO filings encoding ALE process constraints.
Plasma-Enhanced ALE vs. Thermal ALE for HARC Contact Applications
Click any row to explore further.
| Dimension | Plasma-Enhanced (Anisotropic) ALE | Thermal (Isotropic) ALE |
|---|---|---|
| Surface modification (e.g. Cl adsorption) + ion-driven desorption | Sequential thermally driven self-terminating and self-saturating chemical reactions | |
| Anisotropic — directional, vertical etch | Isotropic — conformal, omnidirectional removal | |
| Anisotropic HARC formation in Si, GaN, compound semiconductors | Contact bottom cleaning, gate dielectric trimming, native oxide removal | |
| Low vs. continuous plasma; potential residual ion-induced damage at extreme depths | Damage-free — no plasma exposure; no interface state generation | |
| Monolayer-by-monolayer removal; self-limiting prevents microloading | Sub-angstrom control; Al2O3 demonstrated at 0.8–1.2 Å/cycle at 225–300°C | |
| Cl2/Ar, O2/BCl3 (GaN), acid halide Rf-COX (Kanto Denka Kogyo, 2022 EP) | TMA/HF (Al2O3), acetylacetone/O2 plasma (ZnO) | |
| Lam Research (2017, US), Kanto Denka Kogyo (2022, EP) | Literature (2017, 2018); no dedicated equipment vendor patent in this dataset | |
| Samsung reversed HARC (2023), Synopsys CFET (2024), GAA nanosheet recess | Sub-10 nm channel cleaning, GAA nanosheet dielectric trimming |
Frequently Asked Questions: Atomic Layer Etching for HARC Contacts
ALE uses sequential, self-limiting surface reactions that remove material one atomic layer at a time, preventing the microloading and aspect-ratio-dependent etch rate variation that degrades deep contacts in conventional continuous plasma etching. The self-limiting nature also prevents sidewall damage and profile loss at extreme depths, which are the dominant yield failure modes in HARC contacts.
A reversed HARC structure, as claimed in Samsung’s 2023 US and EP patents, is a semiconductor architecture in which a via extends through the interlayer dielectric (ILD), shallow trench isolation (STI), and the wafer itself to connect a front-side middle-of-line contact to a backside power rail. This represents the most geometrically demanding HARC geometry in current production roadmaps and is required for backside power delivery at the 2 nm node and beyond.
Thermal ALE uses sequential thermally driven chemical reactions — self-terminating and self-saturating — to achieve isotropic, damage-free material removal, with demonstrated sub-angstrom control (0.8–1.2 Å/cycle for Al2O3 at 225–300°C). Plasma-enhanced ALE is anisotropic and directional, using ion bombardment for desorption. Thermal ALE is preferred for contact bottom surface cleaning and gate dielectric trimming where plasma-induced interface state generation must be avoided.
In this dataset, the key assignees are Samsung Electronics (reversed HARC US and EP, 2023), Lam Research (ALE bottom-up fill, 2017 US), GlobalFoundries (HARC metallization 2014, GCIB etch stop 2015, SAC 2015), TSMC (SAC 2001, BEOL air gap 2015), Synopsys (CFET self-limiting etch, 2024 US), Kanto Denka Kogyo (acid halide ALE, 2022 EP), and Micron Technology (sacrificial CVD Ge for VLSI contacts, 1997 US).
ALE is applied to remove thin AlGaN barrier layers in GaN MIS-HEMT gate recess without creating surface damage that degrades channel mobility or breakdown voltage. A 2023 study demonstrates ALE achieving Ra = 0.40 nm surface roughness with 3.7 nm remaining AlGaN layer, 608 mA/mm drain current, and a threshold voltage of +2.0 V. A 2022 study on InAlN/GaN achieves an etch per cycle of 0.15 nm/cycle with RMS roughness of 0.61 nm, superior to continuous etch alternatives.
Synopsys’ 2024 patent introduces a blocking material and self-limiting etch sequence to prevent n/p contact shorting in vertically stacked complementary FETs (CFETs). It represents ALE-inspired design methodology being embedded into design rule checking and process simulation tools — a signal that ALE process concepts are migrating from fab-floor process IP into electronic design automation (EDA), which will increasingly shape what device architectures are manufacturable at advanced nodes.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.