Atomic Layer Etching Sub-5nm — PatSnap Eureka
Atomic Layer Etching: Selectivity at Sub-5nm Patterning
Conventional RIE cannot achieve the surface binding energy discrimination or CD uniformity demanded at sub-5nm nodes. ALE's self-limiting sequential reactions deliver atomic-scale material removal precision — and the patent landscape reveals exactly how the industry is deploying it.
ALE Self-Limiting Cycle — Two-Step Process
Each ALE cycle converts only the outermost atomic layer, then volatilises it — leaving bulk material untouched.
Self-Limiting Surface Chemistry — The Foundation of ALE Selectivity
ALE is distinguished from continuous etching processes by its reliance on sequential, self-limiting surface reactions. In each cycle, a surface modification step chemically converts only the outermost atomic layer(s) of the target material into a weakened intermediate — a "modified layer" — while leaving the bulk unchanged. A subsequent removal step then volatilises exclusively this modified layer, leaving a pristine, unreacted surface for the next cycle.
This self-limitation is the primary source of selectivity: only the modified species are susceptible to removal, and once the modified layer is consumed, the reaction terminates spontaneously. According to PatSnap's patent analytics, Lam Research's directionality-control architecture — filed 2017–2025 across US, CN, TW, KR, SG, and WO jurisdictions — establishes that a bias voltage applied during surface modification controls the conversion depth to at least one monolayer, while the removal step exploits a ligand-exchange reaction to volatilise the modified layer.
The energy framework underlying selectivity is most rigorously quantified in the "Designer ALE" family of patents. The method requires that process conditions for surface modification produce an energy less than the modification energy but greater than the desorption energy, and the removal step must produce an energy greater than the desorption energy but less than the surface binding energy of the material to prevent physical sputtering. By "calculating synergy" across these energy windows, engineers can maximise the process window for ALE and rationally design systems where one material is etched while an adjacent material — with a different surface binding energy — remains untouched. This atomic energy-based framework has been validated on semiconductors (Si, Ge, SiGe, GaN), metals (W, Co, Cu, Ta), dielectrics (SiO2, SiN), and hard masks. Learn more about advanced materials innovation intelligence from PatSnap.
Thermal ALE — the fully isotropic variant — achieves selectivity through sequential gas-phase reactions without plasma. As demonstrated by the University of Colorado, the method involves contacting a metal oxide substrate first with an oxidant to convert the surface, then with a fluorinating agent, with both steps being self-limiting at the monolayer level. Rate enhancement is possible through ligand-exchange reactions in which a metal precursor (e.g., Sn(acac)2 or trimethylaluminum) accepts fluorine from the metal fluoride surface and transfers its ligands to form volatile species such as AlF(acac)2 or AlF(CH3)2.
How ALE Delivers Cross-Material Selectivity at Sub-5nm
Four critical selectivity mechanisms drawn from the patent corpus, each addressing a distinct failure mode of conventional RIE at advanced nodes.
Si-Selective ALE with Metal-Oxide EUV Resist
Tokyo Electron's 2026 filing demonstrates ALE selectively etching Si relative to a metal-oxide photoresist layer formed by EUV lithography. The ALE cycle exposes Si to a halogen-containing gas (CF4 or NF3) without plasma to form a modified Si surface layer, then removes it using an Ar-containing plasma, while the metal-oxide resist — having distinct chemistry — resists attack. An alternative variant pre-treats Si with H-containing plasma to reduce native oxide before fluorination.
Angstrom-level pattern fidelityMonolayer-Thin Etch-Stop Layers
Tokyo Electron's 2022 filing demonstrates that when using an ALE process, a stop layer as thin as approximately one monolayer is sufficient for the etch to self-terminate at the interface between the second film and the first film. This is impossible with RIE, where non-uniformities and micro-loading effects cause the etch front to penetrate stop layers of 3–5nm thickness. The mechanism exploits the chemistry-dependent nature of ALE modification: once the dissimilar stop material is encountered, the surface modification step simply does not produce a reactive intermediate.
Critical for GAA gate dielectric patterningPassivation-Assisted ALE for Sub-15nm Features
For features with widths of 15nm or smaller, Lam Research's 2026 filing adds a passivation step in which the substrate is exposed to a passivating agent plasma to coat sidewall surfaces, preventing lateral modification and limiting active etching to the bottom surface only. This sidewall passivation selectively protects already-etched surfaces while the directional ion plasma continues to drive material removal at the feature floor, avoiding depth-loading entirely.
Eliminates depth loading in narrow featuresRIE Lag Compensation via Quasi-ALE
Tokyo Electron's 2023 filing demonstrates a quasi-ALE (Q-ALE) process exhibiting reverse etch lag combined with a conventional RIE process exhibiting forward lag; the net combination provides a desired, controllable etch lag across all CD values. The Q-ALE process operates as a cyclic deposition-purge-etch sequence that, through its deposition sub-step, preferentially loads narrow features first, producing the reverse lag needed to compensate. This inter-process selectivity — controlling etch rate as a function of CD — cannot be replicated by continuous etch approaches.
Unique to self-limiting cyclic ALEALE Innovation Landscape — Key Data from 50+ Patents
Visualising the assignee distribution, ALE variant coverage, and application domain spread across the analysed patent corpus.
ALE Patent Portfolio by Leading Assignee
Lam Research holds the dominant position; Tokyo Electron is the second most active assignee across the 50+ patent corpus filed 2000–2026.
ALE Process Variant Coverage in Patent Corpus
Plasma (anisotropic) ALE leads coverage; thermal, quasi-ALE, and wet ALE variants address complementary selectivity challenges across the corpus.
Six Key ALE Application Domains at Sub-5nm
From EUV stochastic defect repair to metal interconnect patterning, the patent corpus reveals how ALE is being deployed across the full device stack.
Integrated ALD/ALE for Active CD Correction
Lam Research's 2025 filing describes etching a feature mask pattern to a width narrower than the desired final CD, then using conformal ALD to deposit a passivation layer that expands the mask width to the target value, followed by ALE of the underlying layer to transfer the corrected pattern at precisely the desired width. This ALD-then-ALE scheme decouples lithographic resolution limits from final device CD — all within a single vacuum environment.
EUV Stochastic Defect Correction
EUV lithography at sub-5nm nodes introduces stochastic defects — missing or merged features caused by photon shot noise and resist non-uniformity. Lam Research's cyclic process combines aspect-ratio-dependent deposition (via PECVD) with aspect-ratio-independent ALE. Because partially formed features present a different aspect ratio than fully opened features, the deposition step preferentially fills defective sites while the ALE step uniformly removes material at a constant per-cycle depth, systematically reducing defect density and line-edge roughness (LER).
Contact Patterning in FinFET Processes
TSMC's 2018 filing discloses a method where two sequential ALE steps with different operating parameters open contact vias: the first ALE step removes the bulk of the interlayer dielectric, while a second ALE step with adjusted parameters exposes the source/drain features with minimal over-etch. The parameter-switching capability of ALE enables a progressive, controlled etch stop approach that is impossible with a single-chemistry continuous plasma etch — especially relevant for gate contacts at sub-7nm nodes where the ILD is only a few nanometers thick.
Sidewall Trimming for Sub-Lithographic CDs
SMIC's 2021 and 2023 filings demonstrate using ALE to trim the sidewalls of lithographically defined pattern layers. An organic layer formed on the sidewall reduces the bond energy of outermost atoms below that of the inner lattice atoms. During organic layer removal, the weakened outermost atoms are co-removed at a precisely controlled rate per ALE cycle. By repeating this sequence, sub-lithographic CDs can be achieved with angstrom-level dose control per cycle — directly enabling sub-5nm pitch patterning beyond optical resolution limits.
Key Assignees and Their ALE Innovation Focus Areas
The patent corpus spans seven jurisdictions. Here is how the leading assignees divide the ALE innovation space, based on PatSnap patent analytics.
| Assignee | Primary ALE Focus Areas | Key Jurisdictions | Filing Period | Role |
|---|---|---|---|---|
| Lam Research Corporation | Directionality control, Designer ALE, ALD/ALE integration, passivation-assisted ALE, metal ALE, EUV defect correction | US, CN, TW, KR, SG, WO | 2017–2025 | Dominant |
| Tokyo Electron Limited (TEL) | Quasi-ALE for RIE lag, Si-selective ALE with EUV resist, ultrathin ESL, wet/gas-phase hybrid ALE, fast ALE via ion mass segregation | CN, US, TW | 2016–2025 | 2nd Most Active |
| University of Colorado | Foundational thermal ALE chemistry: sequential oxidation/fluorination, ligand-exchange rate enhancement | US, WO | 2016–2020 | Foundational |
| TSMC | ALE-enabled contact patterning in advanced FinFET / gate-last CMOS; two-step parameter-switching ALE for ILD opening | US | 2018 | Device Mfr. |
| SMIC | ALE sidewall trimming for sub-lithographic CD control; angstrom-level dose control per cycle | US | 2021–2023 | Device Mfr. |
| Beijing NAURA | Apparatus patents for process uniformity via dual-chamber electrode design | CN | 2023 | Regional Equip. |
| Zhejiang Jimai | ALE applied to III-V compound semiconductor patterning | CN | 2024 | Regional Materials |
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Five Trends Shaping the Future of ALE Technology
Analysis of the 50+ patent corpus reveals five key innovation trends identifiable across the filings. First, expansion of ALE from Si and dielectrics to metals, metal oxides, nitrides, and III-V materials — the Designer ALE thermodynamic framework has been validated on semiconductors (Si, Ge, SiGe, GaN), metals (W, Co, Cu, Ta), dielectrics (SiO2, SiN), and hard masks, as noted in Lam Research's 2024 CN filing.
Second, integration of ALE with EUV lithography for stochastic defect repair — the combination of aspect-ratio-dependent deposition and aspect-ratio-independent ALE systematically repairs missing or merged features caused by photon shot noise, addressing a fundamental yield challenge at sub-5nm. According to the Semiconductor Industry Association, stochastic defects are among the top yield limiters at advanced EUV nodes.
Third, passivation-assisted ALE to address depth loading in high-aspect-ratio sub-15nm features — Lam Research's 2026 CN filing places this squarely within the sub-5nm patterning regime. Fourth, ALD/ALE integration for active CD correction without additional photolithography — enabling the final pattern width to be dialled in with sub-angstrom accuracy. The IEEE has documented the growing importance of such atomic-scale process control at advanced nodes.
Fifth, the emergence of "fast ALE" using ion mass segregation and single-process-gas formulations to increase throughput while maintaining self-limiting precision — as recently disclosed in Tokyo Electron's 2025 TW filing on selective ion mass segregation in pulsed plasma ALE. For a broader view of how life sciences and semiconductor innovation intersect in advanced materials, PatSnap provides cross-domain intelligence. See also how PatSnap customers are applying these insights to R&D strategy.
Where ALE Selectivity Is Being Applied Across the Device Stack
From front-end gate patterning to BEOL interconnects, ALE addresses distinct selectivity challenges at each level of the device stack.
ALE Application Domains — Patent Coverage by Stack Level
Gate/channel patterning and EUV integration lead patent coverage; metal interconnects and planarisation represent growing areas.
ALE Patent Filing Jurisdictions in the Corpus
CN and US dominate filing activity; KR, TW, WO, JP, and SG reflect the global strategic breadth of ALE IP protection.
Atomic Layer Etching at Sub-5nm — Key Questions Answered
Conventional reactive ion etching (RIE) cannot achieve the surface binding energy discrimination, critical dimension (CD) uniformity, or etch-depth control demanded at sub-5nm and sub-10nm nodes. ALE operates through sequential self-limiting half-reactions — a surface modification step followed by a targeted removal step — delivering atomic-scale material removal precision and cross-material selectivity that this generation of patterning requires.
The Designer ALE framework requires that process conditions for surface modification produce an energy less than the modification energy but greater than the desorption energy, and the removal step must produce an energy greater than the desorption energy but less than the surface binding energy of the material to prevent physical sputtering. By calculating synergy across these energy windows, engineers can maximise the process window for ALE and rationally design systems where one material is etched while an adjacent material — with a different surface binding energy — remains untouched.
Yes. When using an ALE process, a stop layer as thin as approximately one monolayer is sufficient for the etch to self-terminate at the interface between the second film and the first film. This is impossible with RIE, where non-uniformities and micro-loading effects cause the etch front to penetrate stop layers of 3–5nm thickness.
A method is provided for performing ALE to selectively etch Si relative to a metal-oxide photoresist layer formed by EUV lithography. The ALE cycle exposes the Si substrate to a halogen-containing gas (CF4 or NF3) in the absence of plasma to form a modified Si surface layer, then removes it using an Ar-containing plasma, while the metal-oxide resist — having distinct chemistry — resists attack. This selectivity of Si over metal oxide masks enables pattern fidelity at the angstrom level, where conventional plasma etch would erode the resist and produce linewidth roughness.
Depth loading is the phenomenon where etch products or radical recombination cause the etch rate at the bottom of a narrow feature to decrease relative to the top, producing tapered or incompletely opened features. For features with widths of 15nm or smaller, the disclosed ALE method adds a passivation step in which the substrate is exposed to a passivating agent plasma to coat sidewall surfaces, preventing lateral modification and thus limiting the active etching to the bottom surface only.
The integrated approach etches a feature mask pattern to a width narrower than the desired final CD, then uses conformal ALD to deposit a passivation layer that expands the mask width to the target value, followed by ALE of the underlying layer to transfer the corrected pattern at precisely the desired width. This ALD-then-ALE scheme decouples lithographic resolution limits from final device CD.
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References
- Control of directionality in atomic layer etching — Lam Research Corporation, 2019 (US)
- Control of directionality in atomic layer etching — Lam Research Corporation, 2018 (WO)
- Designer Atomic Layer Etching (设计者原子层蚀刻) — Lam Research Corporation, 2020 (CN)
- Designer ALE and Tantalum ALE (设计者原子层蚀刻和钽的原子层蚀刻) — Lam Research Corporation, 2024 (CN)
- Atomic layer etching processes using sequential, self-limiting thermal reactions comprising oxidation and fluorination — University of Colorado, 2019 (US)
- Atomic layer etching processes using sequential, self-limiting thermal reactions comprising oxidation and fluorination — University of Colorado, 2018 (US)
- Enhancement of thermal atomic layer etching — University of Colorado, 2020 (US)
- Novel methods of atomic layer etching (ALE) using sequential, self-limiting thermal reactions — University of Colorado, 2016 (WO)
- Selective ALE of Si-based materials (Si基材料的选择性原子层蚀刻) — Tokyo Electron, 2026 (CN)
- Method using ultrathin etch-stop layer in selective ALE (在选择性原子层蚀刻中使用超薄蚀刻停止层的方法) — Tokyo Electron, 2022 (CN)
- Atomic layer etching using passivation and directional plasma (使用钝化和定向性等离子体的原子层蚀刻) — Lam Research Corporation, 2026 (CN)
- Atomic layer etching using passivation and directional plasma — Lam Research Corporation, 2025 (TW)
- Method for reducing RIE lag in low-k dielectric etching (用于在低K电介质蚀刻中减少反应离子蚀刻滞后的方法) — Tokyo Electron, 2023 (CN)
- ALD and ALE in a single plasma chamber for CD control (针对关键尺寸控制在单一等离子体室中的原子层沉积和蚀刻) — Lam Research Corporation, 2025 (CN)
- Integrated atomic-scale processes: ALD and ALE (集成原子级工艺：ALD和ALE) — Lam Research Corporation, 2021 (CN)
- Eliminating yield impact of stochastic events in lithography (消除光刻中随机数的收率影响) — Lam Research Corporation, 2020 (CN)
- Semiconductor device and fabrication method therefor — TSMC, 2018 (US)
- Method for forming semiconductor structure — SMIC, 2021 (US)
- Atomic layer etching for subtractive metal etching — Lam Research Corporation, 2021 (KR)
- Systems and Methods for Improving Planarity using Selective Atomic Layer Etching (ALE) — Tokyo Electron, 2022 (US)
- Semiconductor Industry Association (SIA) — semiconductor technology roadmap and advanced node challenges
- IEEE — advanced semiconductor process control and atomic-scale patterning publications
- WIPO — global patent database and international filing statistics
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. Patent analysis conducted via PatSnap Eureka.
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