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Run your analysis now →https://www.patsnap.com/resources/blog/rd-blog/automated-test-equipment-for-soc-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Patent Landscape · Wafer Test & ProbeAutomated test equipment patents for SoC: who holds the claim space and where it is still open
- Concentrated but not locked up. the five leading assignees hold 25.1% of all 5,347 records in scope, and the ranked ten hold 34.2% — a large field with no single gatekeeper.
- Filing has cooled from its 2023 peak. output hit 157 records that year, but 2021-to-2024 activity is down 12% even on complete-year data, before the usual 18-month publication lag understates the last two years further.
- Measurement and data-processing claims dominate. G01R covers 62.0% of records and G06F 42.5%, while control-systems and general semiconductor-device classes sit under 3% each — a visible gap for anyone filing there.
5,347
Published Records
25%
Top-5 Share of All Records
-12%
Filing Growth 2021→2024
US
Leading Jurisdiction
Filing growth compares 2021 (139 records) with 2024 (122) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 5,347 records in scope (CR5), not by the ranked leaders only.
Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Overview
What this landscape covers
This review covers patent families published between 2015 and mid-2026 that describe automated test equipment (ATE) for system-on-chip devices: test program generation, parallel test-site architectures, DUT power delivery, adaptive test flows and coverage measurement. The scope is defined by a search string combining core ATE terms with specific technical mechanisms, so the 5,347 records in scope are records that name both the equipment and a concrete test technique, not every patent that merely mentions a tester.
Filing is dominated by a handful of large test, EDA and semiconductor firms alongside a long tail of single- or few-filing entrants, and the technology composition skews heavily toward electrical measurement and digital data processing rather than the mechanical or control-systems side of test.
Filing activity and technology mix, 2017–2026
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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The numbers
Filing trend and technology composition
Two views of the same 5,347-record dataset: how filing volume has moved year over year, and which IPC subclasses the claims actually sit in.
Filing trend, 2017–2026
Annual filings rose from 129 in 2017 to a peak of 157 in 2023, then eased to 122 in 2024 — a 12% decline over the 2021-to-2024 span using the last complete years. 2025 and 2026 show far fewer records (down to 9 in 2026), but that reflects the roughly 18-month lag between filing and publication, not a sudden stop in filing activity.
Technology composition by IPC subclass
G01R (electric and magnetic measurement) appears in 62.0% of records and G06F (digital data processing) in 42.5%, confirming that most claims are written around measurement and software/data handling rather than the physical test cell. Memory-specific test (G11C, 11.2%) and semiconductor device structure (H01L, 8.5%) are secondary clusters, while control/regulating systems (G05B, 2.1%) and general semiconductor devices (H10D, 1.9%) are thin — each record can carry more than one class, so these shares do not sum to 100%.
Shares are the percentage of the 5,347 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.
Go deeper on Automated Test Equipment for SoC with Eureka
This page is one run against one query. Ask Eureka your own question about automated test equipment for soc and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative filing
A representative claim construction
Representative record · WO2021023372A1
Automated test equipment with shared memory access to the device under test
ADVANTEST CORPORATION
The filing describes an ATE architecture in which a processing unit executes code from a program and/or data memory and establishes communication with the device under test through a first interface — commonly a debug interface or debug access port — used for low-data-rate control access, alongside additional interfaces for higher-throughput test traffic.Filed by Advantest Corporation; abstract trimmed for length — full claim set available in Eureka.
Most-cited records in this dataset
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20050023656A1 | Vertical system integration | 785 |
| 2 | US6642744B2 | Customizable and programmable cell array | 530 |
| 3 | US6721941B1 | Collection of timing and coverage data through a debugging interface | 499 |
| 4 | US6819136B2 | Customizable and programmable cell array | 490 |
| 5 | US5208765A | Computer-based method and system for product development | 489 |
| 6 | US6760903B1 | Coordinated application monitoring in a distributed computing environment | 471 |
| 7 | US6331790B1 | Customizable and programmable cell array | 392 |
| 8 | US5827070A | System and methods for computer based testing | 371 |
| 9 | US7402897B2 | Vertical system integration | 352 |
| 10 | US20080237591A1 | Vertical system integration | 347 |
Citation counts favour older filings that have had more time to accumulate references, so treat this table as a signal of past influence rather than of what matters today.
Each row carries its publication number; clicking a row searches Eureka by that number.
Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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What the data implies for filing strategy
Three patterns worth acting on rather than just noting.
Concentration
25.1% / 5,347
top 5 share of all records
The top of the field is broad, not narrow
The five leading assignees together account for 25.1% of all 5,347 records, and the ranked ten reach 34.2% — high enough to signal real prior-art density around core ATE architecture, but low enough that no single company can claim the whole field.
Check freedom-to-operate against the leaders individually, not the category as a whole.
Trend
-12%
2021→2024 filing change
Volume has eased from its 2023 peak
Filings peaked at 157 records in 2023 and the 2021-to-2024 window is down 12% on complete-year data. That is a cooling from peak, not a collapse — and the two most recent years are undercounted because publication lags filing by around 18 months.
Re-check 2025–2026 volumes again once those cohorts finish publishing.
Composition
62.0% / 42.5%
G01R vs G06F share
Measurement and data-processing claims crowd the space
G01R (measurement) and G06F (data processing) between them touch a large majority of records, while control-systems (G05B) and general semiconductor-device (H10D) classes sit under 3% each — the latter two are comparatively open.
A claim written purely around control-loop test sequencing has fewer direct neighbors than one written around measurement circuitry.
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Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to automated test equipment for soc, with the prior art for and against each one.
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Assignee landscape
Who is filing, and where the momentum has gone quiet
The ranking covers 100 companies tracked by the data endpoint — not a top-50 or top-100 cut of the whole field, but the full ranked set it returns. Filing is led by a mix of dedicated ATE vendors, EDA software firms and large chipmakers, with a long tail of single-digit filers behind them.
Leader
454 records
leading assignee
One vendor sets the pace
The top-ranked assignee holds 454 records, well ahead of fifth place at 122 and tenth place at 82 — a steep drop-off after the leader rather than a gradual taper.
Its claim footprint is the first one to check before filing in core ATE architecture.
Long tail
100 ranked
assignees in the ranking
A wide base of smaller filers
Beyond the ranked ten, the field spreads across many test-equipment, EDA and chip companies with modest filing counts each, consistent with a technology area still being built out by many hands rather than settled by a few.
Watch for consolidation through co-assignee filings, which already show up between a few EDA-adjacent pairs.
Momentum
0 in latest year
several leaders' recent activity
Recent-year activity has gone quiet for the biggest names
Several of the largest historical filers show zero records and steep year-over-year declines in the most recent tracked year — a pattern that is at least partly the publication-lag effect rather than firms stepping away from the field.
Confirm against 2024 full-year filings before reading this as strategic retreat.
Recent-year filing momentum by assignee
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | -100% |
| Advantest Corporation | 0 | -100% |
| Texas Instruments Inc. | 0 | -100% |
| Agilent Technologies Inc. | 0 | — |
| Intel Corporation | 0 | -100% |
| Mentor Graphics (Siemens EDA) | 0 | — |
| Cadence Design Systems Inc. | 0 | — |
| Hitachi, Ltd. | 0 | — |
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Next steps
Where to take this analysis
The dataset points to a field with a clear leader, a wide base of smaller filers and a few visibly thinner claim clusters. Turning that into a filing or freedom-to-operate decision needs a closer read of the actual claims.
Map claims against the leader's portfolio
Before filing in core ATE architecture — shared memory access, debug interfaces, program execution — pull the leading assignee's full claim set rather than relying on the aggregate share.
Explore assignee portfolios in Eureka →Stress-test the under-claimed branches
Control-systems and general semiconductor-device classes sit under 3% of records each; confirm whether that reflects real white space or simply a different classification habit before committing to a claim strategy there.
Run a white-space search in Eureka →Source: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ
Common questions about this landscape
The ranked leader holds 454 records against a fifth-place figure of 122 and a tenth-place figure of 82, so there is a clear leader followed by a steep drop-off rather than a gradual taper. The top five combined hold 25.1% of all 5,347 records in scope, and the top ten hold 34.2% — concentrated at the top but with a long tail of over ninety other ranked assignees behind them. The field includes dedicated ATE vendors, EDA software firms and large chipmakers rather than being dominated by one industry segment.
Filing rose from 129 records in 2017 to a peak of 157 in 2023, then eased to 122 in 2024 — a 12% decline over that 2021-to-2024 span using complete-year data. The much lower counts shown for 2025 and 2026 are not a real collapse: publication typically lags filing by around 18 months, so the most recent one to two years are always undercounted in any patent trend. Treat the 2024 figure, not the raw 2026 figure, as the best recent read on activity.
Electric and magnetic measurement (IPC class G01R) appears in 62.0% of the 5,347 records in scope, and digital data processing (G06F) in 42.5% — together the two dominant clusters. Memory-specific test (G11C) and semiconductor device structure (H01L) form smaller secondary clusters at 11.2% and 8.5% respectively. Control and regulating systems (G05B) and general semiconductor devices (H10D) sit under 3% each, marking them as comparatively thin claim areas relative to the measurement and data-processing core.
The thinnest IPC clusters in this dataset are control and regulating systems (G05B, 2.1% of records) and general semiconductor devices (H10D, 1.9%), both well behind the measurement and data-processing classes that dominate filing. Sub-areas worth a closer look include adaptive test-sequencing control loops, DUT power delivery regulation circuits and parallel test-site scheduling algorithms, none of which show the same filing density as core measurement or debug-interface claims. That said, thin classification does not guarantee an open field — it can also reflect a different way of tagging similar inventions, so a freedom-to-operate check is still needed before relying on it.
WO2021023372A1, filed by Advantest Corporation, describes an automated test equipment architecture where a processing unit executes code from a program and/or data memory and communicates with the device under test through a first interface — typically a debug interface or debug access port — intended for lower-data-rate control access, alongside separate higher-throughput interfaces. It sits squarely in the shared-memory and debug-access corner of ATE architecture rather than covering test methodology broadly. Anyone designing a similar shared-memory DUT communication scheme should review its full claim set rather than relying on the abstract alone.
Answers are grounded in the same dataset. Derived from a Patsnap search on Automated Test Equipment for SoC covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.