Backside Illuminated CMOS Image Sensor Patents 2026
Backside Illuminated CMOS Image Sensor Patents
BSI CMOS image sensors have become the dominant architecture as pixel pitches shrink below 2 µm. Innovation now centres on 3D stacked integration, spectral extension into infrared and X-ray ranges, and global shutter capability.
How BSI Architecture Transformed CMOS Image Sensor Performance
Backside illuminated CMOS image sensors reposition the photodiode array so incident light strikes the photodiode before encountering metal wiring or dielectric layers. The process involves thinning the silicon substrate to a few micrometers, bonding it to a handle wafer, and forming color filters and microlenses on the exposed back surface, eliminating the optical obstruction inherent in front-side illuminated designs.
This configuration enables high quantum efficiency across visible, near-infrared, and soft X-ray spectral bands. The dataset spans over 70 distinct patent records and technical papers from 2008 to 2026, covering photodiode architecture and passivation, pixel isolation and crosstalk suppression, spectral extension, 3D stacking with global shutter, and manufacturing process innovations including TMAH thinning and high-K dielectric isolation.
The foundational period from 2007 to 2010 established core BSI concepts, with Teledyne Scientific and OmniVision Technologies securing early positions in pinned photodiode BSI and backside passivation. The development period from 2011 to 2016 saw the largest filing density, with Samsung, TSMC, SK Hynix, and Aptina extending the technology into vertical pixel stacks, capacitor integration, and global shutter architectures.
In this dataset, OmniVision Technologies is the most prolific assignee, with filings spanning infrared sensitivity, dark current reduction, and vertical pixel stacks from 2009 through 2022. Intellectual Ventures II LLC and TSMC account for the next largest shares of retrieved records, while Chinese mainland foundries including Shanghai Huali and Huaian Imaging represent a growing presence in post-2017 filings in retrieved records.
BSI Patent Filing Trends and Assignee Distribution
Filing activity in this dataset clusters most densely in the 2011–2016 development period, with continued activity through 2026 focused on manufacturing maturity and advanced integration. The assignee base spans US, Korean, Taiwanese, Chinese, and European entities.
Top Assignees by Filing Count — BSI CMOS Image Sensor (Retrieved Records)
OmniVision Technologies accounts for the largest share of retrieved records in this dataset, followed by Intellectual Ventures II LLC and TSMC, reflecting concentrated foundational IP ownership in BSI passivation and process architectures.
↗ Click bars to exploreBSI Patent Filing Activity by Era — Retrieved Records
The 2011–2016 development period contains the highest filing density in this dataset, with the 2017–2022 consolidation period second, and 2023–2026 emerging directions filings reflecting manufacturing maturity signals rather than architectural reinvention.
↗ Click bars to exploreBSI CMOS Sensor Deployment Across Key Application Areas
BSI CMOS image sensors appear across consumer electronics, scientific imaging, automotive vision, and high-speed industrial applications. Each domain places distinct demands on pixel architecture, spectral range, and readout speed.
Smartphone & Consumer Camera Imaging
The largest application domain in the dataset, with OmniVision Technologies (Shanghai), Samsung, DB Hitek, SK Hynix, and Huaian Imaging all targeting smartphone and digital camera markets. Huaian Imaging Device Manufacturer Corporation (2019, US) explicitly cites improved low-illumination performance as the primary commercial driver. Powerchip Semiconductor’s 2025 filings list smartphones, digital cameras, and biomedical devices as primary use cases for its full well capacity and dynamic range improvements.
Consumer ElectronicsScientific & Medical Imaging Instruments
A soft X-ray BSI sensor paper in the dataset achieves greater than 90% quantum efficiency across 80–1000 eV, with 5 nm dead-layer thickness, 9.5 µm silicon layer, and 2.5 e− rms readout noise, targeting synchrotron, EUV lithography metrology, and X-ray free electron laser experiments (2019). A high-definition CMOS endoscope camera design employing 720P sensors with LVDS output also appears in the dataset. Powerchip Semiconductor explicitly lists medical endoscopy as a use case in its 2025 filings.
Scientific ImagingAutomotive Vision & Machine Vision
While no patent in this dataset explicitly claims automotive labeling, TSMC’s global shutter BSI filings from 2016–2018 directly address rolling shutter distortion artifacts, a critical requirement for autonomous vehicle cameras and industrial machine vision systems. The 3D stacked voltage domain global shutter sensor literature from 2020 explicitly mentions motion artifact elimination as a key benefit. TSMC’s vertical transfer gate structure (2016 US filing) improves global shutter efficiency in BSI configuration for such applications.
Automotive & Machine VisionHigh-Speed Industrial & Scientific Imaging
A 3D stacked BSI sensor with pixel-wise Si trench capacitor analog memory achieves 125 Mfps with 368-frame record length (published 2020), targeting non-repeatable transient phenomena such as combustion, plasma physics, crash testing, and laser-matter interaction. A separate 2018 publication demonstrates 5 Mfps with 52 frames of in-pixel digital memory via 3D stacking, with BSI providing improved fill factor and wide-spectrum sensitivity. These architectures represent the performance frontier of 3D stacked BSI integration.
High-Speed ImagingLeading Patent Assignees in BSI CMOS Image Sensors (Retrieved Records)
In this dataset, OmniVision Technologies holds the largest number of retrieved records, spanning infrared sensitivity, dark current reduction, and vertical pixel stacks across US and EP jurisdictions from 2009 through 2022. Intellectual Ventures II LLC and TSMC account for the next largest shares of retrieved records, with Chinese mainland and Korean foundries representing a growing presence in post-2017 filings in retrieved records.
Top Assignees by Estimated Filing Count — BSI Patents (Dataset Snapshot)
↗ Click bars to exploreOmniVision Technologies, Inc.
The most prolific assignee in this dataset, with filings spanning infrared sensitivity, dark current reduction, backside passivation, vertical pixel stacks, and circuit/photo sensor overlap across US, WO, and EP jurisdictions from 2009 through 2022. Key patents include the infrared detecting layer architecture (WO 2009), the vertical pixel sensor for Bayer-filterless color separation (US 2009), and dark current suppression via dopant confinement (US 2011). Multiple continuation families have been maintained through 2022.
United StatesIntellectual Ventures II LLC
Holds a substantial BSI portfolio concentrated on backside passivation layer architecture and transparent conductive layer voltage biasing for interface state dark current suppression, spanning US and EP jurisdictions from 2009 through 2018. The foundational transparent conductive backside bias architecture (US 2009) was replicated and maintained in multiple re-filings through 2018, including active families at 2011 and 2018 publication dates. Patents originate from Korean inventors with KR priority claims and have been actively maintained through multiple continuation filings.
United StatesFive Forward-Looking BSI Technology Directions (2022–2026)
Based on filings with publication dates from 2022 onward in this dataset, five distinct forward-looking directions are identifiable, ranging from optical path engineering to manufacturing reliability — signalling a late-growth to early-maturity transition.
Light Scattering Layers for Wavelength-Selective Sensitivity
DB Hitek’s 2022-priority filings (published 2023 and 2026) introduce internal scattering layers within the BSI substrate that cause incident light to traverse a path length exceeding substrate thickness. By varying scattering layer depth, per-color-filter sensitivity can be tuned without changing photodiode doping profiles. This approach enables wavelength-selective enhancement independent of pixel geometry.
High-K Dielectric Metal Grid for Combined Electrical and Optical Isolation
Shanghai Huali Integrated Circuit Corporation’s 2026 US filing introduces grid trenches filled with a high-K dielectric layer, an insulating layer, and a metal core layer within the pixel substrate. This architecture achieves simultaneous electrical isolation and optical crosstalk reduction within a single process step. The approach targets both quantum efficiency improvement and stress reliability in high-volume BSI production.
BSI vs FSI CMOS Image Sensor Architecture: Key Dimensions
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| Dimension | BSI (Backside Illuminated) | FSI (Front-Side Illuminated) |
|---|---|---|
| Light path to photodiode | Light strikes photodiode directly from back surface before any metal layers | Light must pass through metal interconnect layers M1/M2 and dielectrics before reaching photodiode |
| Quantum efficiency | High QE across visible, NIR, and soft X-ray (>90% QE demonstrated at 80–1000 eV) | Lower QE, especially in blue and NIR bands, due to metal layer absorption and reflection losses |
| Fill factor | Improved fill factor; metal wiring does not reduce photon-sensitive area | Reduced fill factor as pixel pitch shrinks below 2 µm due to metal layer obstruction |
| Dark current management | Requires dedicated passivation strategies (transparent conductive layer, doping profiles) to manage thinned back surface states | Dark current managed through standard front-side isolation; less surface-state challenge at back |
| Manufacturing complexity | Requires substrate thinning (TMAH process), wafer bonding to handle substrate, back-surface passivation, and color filter/microlens formation on back | Conventional CMOS process flow; no substrate thinning or wafer bonding required |
| 3D stacking compatibility | Inherently compatible with wafer-bonded logic/memory tier; enables global shutter, high dynamic range, and >100 Mfps burst operation | Less suited to wafer-bond stacking due to front-side wiring orientation |
| Crosstalk management | Requires DTI, metal grid, high-K dielectric isolation, and scattering layers as pixel pitch compresses | Crosstalk managed by standard well isolation; less critical at larger pixel pitches |
| IP landscape maturity | Foundational IP locked by OmniVision, Intellectual Ventures II LLC, and TSMC (2009–2018 core families); active continuation families | Mature and widely licensed; less active patent prosecution in recent filings in this dataset |
Frequently Asked Questions: BSI CMOS Image Sensor Patents
A backside illuminated CMOS image sensor repositions the photodiode array to receive light from the substrate’s back surface, eliminating signal obstruction from front-side metal interconnects (layers M1 and M2) and dielectrics. This improves quantum efficiency, fill factor, and low-light performance compared to conventional front-side illuminated architectures, where metal wiring blocks the photon path to the photodiode.
In this dataset, OmniVision Technologies is the most prolific assignee, with filings spanning infrared sensitivity, dark current reduction, vertical pixel stacks, and passivation from 2009 through 2022. Intellectual Ventures II LLC holds a substantial BSI passivation portfolio across US and EP jurisdictions from 2009–2018. TSMC concentrates on global shutter BSI, wafer bonding, and advanced process nodes from 2011–2018. DB Hitek is active from 2019–2026 on scattering layers and manufacturing processes.
The foundational challenge is managing the high density of surface states on the thinned back surface, which generates dark current and degrades signal-to-noise ratio. Solutions in retrieved records include doping profile engineering, transparent conductive layer voltage biasing (Intellectual Ventures II LLC), and designated dopant confinement in the seed layer (OmniVision, 2011). More recent filings (Wuhan Xinxin, 2025) address stress-relief in back-surface metal wires as a manufacturing yield and reliability challenge.
Stacking a thinned BSI pixel wafer on a dedicated logic or memory wafer via wafer bonding or micro-bump interconnects enables global shutter, high dynamic range, and burst-rate operation not achievable in single-wafer designs. A 45 nm/65 nm stacked BSI sensor achieving 80 dB single-exposure high dynamic range global shutter operation was published in 2020. A separate publication from 2020 demonstrates 125 Mfps with 368-frame record length using BSI combined with in-pixel Si trench capacitor analog memory.
BSI architecture inherently improves long-wavelength sensitivity by removing the front-side metal absorption path. Retrieved records cover visible, near-infrared (NIR), short-wave infrared (SWIR), and soft X-ray ranges. A soft X-ray BSI sensor paper demonstrates greater than 90% quantum efficiency across 80–1000 eV with 5 nm dead-layer thickness and 2.5 e− rms readout noise, targeting synchrotron, EUV lithography metrology, and X-ray free electron laser experiments.
The most recent filings in this dataset include: DB Hitek’s light scattering layers for extended optical path and wavelength-selective sensitivity (priority 2022, published 2023–2026); Shanghai Huali’s high-K dielectric metal grid isolation for simultaneous electrical and optical isolation (2026, US); Wuhan Xinxin’s stress-relief slots in BSI metal wires for reliability (2025, CN); LFoundry’s common-voltage backside biasing for photon detection efficiency (2025, US); and Powerchip Semiconductor’s full well capacity and dynamic range optimisation for sub-3 µm BSI pixels (2024–2025, US).
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.