Backside Power Delivery Network 2026 — PatSnap Eureka
Backside Power Delivery Network Technology Landscape 2026
BSPDN relocates power distribution rails to the wafer’s back-side, resolving front-side metal congestion and IR-drop losses that have become critical bottlenecks at sub-3nm nodes. This report maps the patent corpus spanning IBM, AMD, and Samsung across fabrication methods, programmable PDN architectures, and backside packaging integration.
Decoupling Power from Signal: The BSPDN Architecture
Backside Power Delivery Network (BSPDN) technology represents a fundamental architectural shift in semiconductor design, relocating power distribution rails from the transistor front-side — where they compete with signal routing — to the wafer’s back-side. This enables simultaneous improvements in power delivery efficiency, signal routing density, and overall chip performance-power-area (PPA) metrics.
The shift is driven by the scaling limits of sub-3nm process nodes, where front-side metal congestion and IR-drop losses have become critical bottlenecks. BSPDN fundamentally decouples power delivery from signal routing by placing a dedicated power distribution network on the opposite (back) side of the silicon wafer from the front-side interconnect stack.
Key structural mechanisms identified across retrieved patents include backside through-silicon contacts connecting active device regions directly to back-side metal power rails, virtual power supply constructs enabling simulation and verification of back-side power topologies, sidewall power tracks routing power vertically from the back-side PDN to the chip package, and three-dimensional programmable PDN architectures combining back-side power with front-side routing resistance management. The PatSnap Analytics platform enables systematic landscape analysis across these structural dimensions.
The technology is anchored in the need to improve the PPA metric, identified as the primary driver in multiple retrieved patents. By separating power and signal domains, BSPDN reduces IR-drop, lowers interconnect resistance, and frees front-side routing tracks for signal lines — directly enabling higher transistor density at advanced nodes. Academic context from the 2021 literature survey on Power Delivery Networks for Embedded Mobile SoCs confirms that conventional off-chip and in-package PDN architectures were already reaching their limits, contextualising why the wafer-backside approach has emerged as the dominant research direction post-2022. The IEEE has published extensive foundational work on PDN design constraints that underpin these developments.
From Foundational Filings to Active Grants: 2024–2026
The BSPDN patent corpus in this dataset is concentrated entirely in 2024–2026, indicating the field is in early-to-mid commercialisation stage with IBM’s 2026 VTFET grant already in active status.
IBM Establishes Core Structural Primitives
International Business Machines Corporation filed multiple patents establishing core structural primitives — backside source/drain contacts for Vertical-Transport Field-Effect Transistors (VTFETs) and virtual power supply constructs through the wafer backside. These represent the enabling fabrication methods underpinning the entire field. Filings span both US and WO jurisdictions.
IBM · US + WO · 3 filingsAMD and Samsung Enter with Differentiated Architectures
Advanced Micro Devices filed a programmable 3D PDN architecture combining back-side power with front-side resistance management. Samsung Electronics filed a backside package architecture integrating BSPDN with memory modules. IBM also filed its sidewall power connection patent addressing the critical packaging interface challenge for volume production.
AMD + Samsung + IBM · 2025IBM’s VTFET Patent Reaches Active Grant Status
IBM’s most recent grant covers sidewall power connections from the BSPDN to the chip package — addressing the critical packaging interface challenge that must be solved for volume production. The 2026 VTFET backside contact patent is listed as active, signalling that BSPDN IP is moving from pending to enforceable status and raising urgency for competitors and ecosystem participants.
IBM · US · Active grant · 2026Literature Baseline Confirms PDN Architecture Limits
The 2021 literature record on Power Delivery Networks for Embedded Mobile SoCs provides an academic baseline confirming conventional off-chip and in-package PDN architectures were already reaching their limits. The FlexWatts hybrid PDN literature (2020) documents the energy-efficiency variance problem across PDN architectures that BSPDN is designed to resolve.
Literature · 2020–2021 baselineFour Structural Approaches to Backside Power Delivery
The 7 BSPDN-relevant patents organise into four distinct technology clusters spanning fabrication, design verification, programmable control, and packaging integration.
Filing Distribution by Technology Cluster
VTFET/Backside Contacts and Package Architecture each account for the largest share of filings in this dataset.
Jurisdiction Coverage by Assignee
US jurisdiction dominates with 6 of 7 relevant filings. Samsung holds the only EP-jurisdiction BSPDN patent in this dataset.
From Device Contacts to Programmable Control to Package Integration
The four BSPDN clusters represent a vertical stack from transistor-level fabrication through architecture-level programmability to package-level integration.
BSPDN Across HPC, Logic-Memory, and Advanced Transistors
Three primary application domains emerge from the retrieved patents, each addressed by a distinct assignee and structural approach.
| Application Domain | Lead Assignee | Key Patent | BSPDN Role | Jurisdiction |
|---|---|---|---|---|
| HPC & Data Center Processors | Advanced Micro Devices, Inc. | Programmable 3D PDN Architecture | Per-domain power management in multi-core processors and SoCs; workload-aware voltage regulation | US, WO |
| Logic-Memory Integration | Samsung Electronics Co., Ltd. | Backside Package Architecture | Enables near-memory computing and high-bandwidth memory-on-logic stacking via BSPDN co-integration with memory modules | US, EP |
| Advanced Logic Transistors (VTFET/GAA) | International Business Machines Corporation | VTFET Backside Source/Drain Connections | Integral structural element of VTFET and Gate-All-Around nanosheet architectures at 2nm and below | US, WO |
IP Positioning, Freedom-to-Operate, and Emerging White Spaces
The concentration of foundational BSPDN IP in three assignees creates distinct strategic considerations for new entrants, EDA vendors, and packaging specialists.
IBM Holds Broadest Foundational IP Position
IBM’s portfolio spans fabrication processes, device structures (VTFET), virtual modelling methods, and packaging interfaces. Any entity commercialising BSPDN at advanced nodes should conduct freedom-to-operate analysis against IBM’s portfolio, particularly the VTFET backside contact claims (US active grant, 2026).
AMD’s Programmable PDN Layer is Strategically Durable
AMD’s programmable PDN architecture claims programmability and control architecture rather than the physical structure — a framing that is strategically durable across multiple process generations and foundry partners, consistent with its position as a fabless chip designer.
Three Forward-Looking Directions from 2025–2026 Filings
The most recent filings signal distinct trajectories for BSPDN innovation: packaging integration, adaptive control, and heterogeneous memory co-integration.
Sidewall and Edge Packaging Integration
IBM’s sidewall power track patent directly addresses the last-mile connectivity problem: how to route power from the back side of the die to the package substrate without requiring through-silicon vias in the active area. The sidewall track that wraps around the chip edge is a novel packaging-compatible solution, representing the most recently filed structural innovation in this dataset. See also the PatSnap materials and process solutions for adjacent packaging research.
IBM · US · 2025Programmable and Adaptive PDN Control
AMD’s introduction of a programmable BSPDN — one that can be actively adjusted based on workload or operating conditions — moves the field beyond static structural improvements toward dynamic, software-configurable power delivery. This direction aligns with increasing interest in workload-aware voltage regulation. The PatSnap Analytics platform enables tracking of this emerging sub-domain. Research from ACM has documented the theoretical basis for workload-aware PDN optimisation.
AMD · WO · 2025BSPDN-Memory Co-Integration for System-Level Stacking
Samsung’s backside package architecture couples BSPDN directly with memory modules, representing an evolution from chip-level BSPDN to package-level heterogeneous integration. This direction is consistent with the broader industry push toward chiplet ecosystems and 3D-stacked architectures. JEDEC standards for high-bandwidth memory interfaces are directly relevant to this integration pathway.
Samsung · EP · 2025Adjacent Claim Spaces for New Entrants
The transition from research to active grants signals that BSPDN IP is moving from pending to enforceable status. New entrants — particularly EDA vendors, packaging specialists, and fabless AI chip companies — face a narrow window to establish non-overlapping claims in design automation, thermal management integration, and BSPDN-to-advanced-packaging co-design. The PatSnap customer case studies document how IP teams navigate these white-space opportunities. WIPO PCT filings data provides additional context on global protection strategies.
EDA · Packaging · AI ChipsBackside Power Delivery Network — key questions answered
A Backside Power Delivery Network (BSPDN) relocates power distribution rails from the transistor front-side to the wafer’s back-side, enabling simultaneous improvements in power delivery efficiency, signal routing density, and overall chip performance-power-area (PPA) metrics.
At sub-3nm process nodes, front-side metal congestion and IR-drop losses have become critical bottlenecks. BSPDN decouples power delivery from signal routing, reducing IR-drop, lowering interconnect resistance, and freeing front-side routing tracks for signal lines — directly enabling higher transistor density.
Three assignees account for all 7 BSPDN-relevant patents in this dataset: International Business Machines Corporation (5 filings, US and WO), Advanced Micro Devices Inc. (2 filings, US and WO), and Samsung Electronics Co. Ltd. (2 filings, US and EP).
The four main clusters are: (1) Backside Source/Drain Contacts and VTFET Integration, (2) Virtual Backside Power Supply and Fabrication Methods, (3) Programmable 3D PDN with Front-Side/Back-Side Co-Management, and (4) Backside Package Architecture and Sidewall Power Interconnect.
BSPDN targets three primary domains: High-Performance Computing and Data Center Processors (AMD’s programmable 3D PDN), Logic-Memory Integration (Samsung’s backside package architecture co-integrating BSPDN with memory modules), and Advanced Logic Transistors including VTFET and Gate-All-Around architectures (IBM’s filings).
Three forward-looking directions emerge from 2025–2026 filings: (1) Sidewall and Edge Packaging Integration — IBM’s sidewall power track addressing last-mile connectivity, (2) Programmable and Adaptive PDN Control — AMD’s workload-aware dynamic power delivery, and (3) BSPDN-Memory Co-Integration for System-Level Stacking — Samsung’s heterogeneous package architecture.
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