Backside Power Delivery Patents: Who Leads, Trends 2026
- Filing activity peaked in 2021 at 11 families and has flattened since, with the 2022 midpoint matching the peak rather than extending it — this is a technology whose core claim space was staked out early, not one still accelerating.
- Momentum has stalled across every major assignee tracked in the dataset, including Samsung, IBM, Tokyo Electron and TSMC, each showing 0 filings in the latest tracked year — a sign the field is between generations rather than abandoned.
- Receiving-office filings concentrate heavily in the United States (39 of the tracked records), with Europe, Taiwan, WIPO, China and Japan each holding single-digit shares — a narrow filing footprint outside the US and EPO.
What backside power delivery patents actually cover
Backside power delivery networks move power rails and vias from the front-side interconnect stack to the wafer backside, freeing routing congestion for signal layers. The dataset tracked here spans 62 patent families filed between 2015 and 2026, concentrated under H01L semiconductor device classifications, with a substantial secondary cluster in H10W and a smaller presence in H10D general semiconductor device manufacture. The claims cluster around buried power rails, nano through-silicon vias, wafer bonding and thinning steps, and IR-drop mitigation — the mechanical and electrical problems that arise once power delivery is separated from the transistor layer.
Because publication lags filing by roughly 18 months, the apparent drop-off in the most recent years understates real filing activity — 2025 and 2026 figures will fill in as later publications surface. Even accounting for that lag, the plateau after 2021 across nearly every tracked assignee suggests the foundational claim territory in this niche was staked early, with incremental refinement now dominating over new architectural filings.
Filing trend and technology composition
Two views of the same 62-family dataset: how filing activity moved year over year, and how those families distribute across IPC subclasses.
A peak in 2021, then a plateau
Filings rose from zero in 2017 to a peak of 11 families in 2021, then held near that level through the 2022 midpoint rather than continuing to climb — a flat-to-declining trend line rather than a growth curve. Given the 18-month publication lag, the tail years of this trend are the least reliable part of the chart.
H01L dominates, with H10W a strong second
Every tracked family sits under H01L (semiconductor devices), and 41 of the 62 also carry an H10W classification, pointing to heavy overlap between core device claims and the newer wafer-level processing subclass. H10D, G06F and H10B appear only marginally, meaning most inventive activity is being claimed as core device architecture rather than as adjacent process or data-processing subject matter.
Shares are the percentage of the 62 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Backside Power Delivery Networks with Eureka
This page is one run against one query. Ask Eureka your own question about backside power delivery networks and every answer comes back with the patent numbers behind it.
Try EurekaThe records anchoring this landscape
EP4109523B1 — buried power rail with a silicide layer for well biasing
Filed by Intel Corporation and granted in December 2025, this record claims a buried power rail structure incorporating a silicide layer used for well-bias delivery — a refinement aimed at reducing contact resistance at the rail-to-substrate interface.Grant date, assignee and publication number are rendered from the underlying record; the summary above reflects only what the title and classification indicate.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US9570395B1 | Semiconductor device having buried power rail | 122 |
| 2 | US20200266169A1 | Replacement buried power rail in backside power delivery | 82 |
| 3 | US20240186248A1 | Backside power delivery network | 76 |
| 4 | US9331062B1 | Integrated circuits with backside power delivery | 71 |
| 5 | US20220181258A1 | Power-tap pass-through to connect a buried power rail to front-side power distribution network | 57 |
| 6 | US20200373241A1 | Power distribution network using buried power rail | 27 |
| 7 | US20200373240A1 | Design applications of buried power rails | 25 |
| 8 | US10886224B2 | Power distribution network using buried power rail | 18 |
| 9 | US20240128150A1 | Semiconductor package structure for enhanced cooling | 12 |
| 10 | US20220384345A1 | Through silicon buried power rail implemented backside power distribution network semiconductor architecture … | 10 |
Citation counts favour older records within any searched corpus — treat these as markers of influence on later filings, not as a ranking of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three findings from the dataset that matter more for strategy than the raw counts alone.
The growth phase has already happened
Filings climbed to 11 in 2021 and have not exceeded that level since, with 2022 matching rather than extending the peak. New entrants filing broad architectural claims now compete against a already-dense prior art layer rather than open ground.
Claims are being written as core device architecture
Two-thirds of the dataset carries both H01L and H10W classifications, meaning most inventive activity ties buried-rail and nano-TSV structures directly to device architecture rather than to standalone process claims — a signal that differentiated process-only filings remain comparatively rare.
Every major filer has gone quiet at once
Samsung, IBM, Tokyo Electron and TSMC all show zero filings and -100% year-on-year change in the latest period. Given the publication lag, this likely reflects filings still working through the pipeline rather than a genuine exit from the space — but it also means the public claim record is temporarily thin.
Filing strategy is narrowly concentrated
The United States receives well over half of all tracked filings, with Europe, Taiwan, WIPO, China and Japan trailing far behind in single digits. A defensive filing strategy built only around US and EPO coverage would miss a meaningful share of parallel Taiwan filings, where foundry-adjacent players are active.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to backside power delivery networks, with the prior art for and against each one.
Who is active, and where the gate is thin
Filing activity concentrates among a small group of device makers and foundry-equipment suppliers, with co-assignment patterns pointing to a handful of tight collaborations rather than a broad ecosystem.
Samsung, IBM, TSMC and Tokyo Electron anchor the field
These four organisations, alongside ND-Hi Tech Lab and Etron Technology, make up the assignees with tracked recent-year momentum — all currently at zero filings in the latest period, consistent with the broader plateau seen since 2021.
Collaborations are narrow and specific
The strongest pairing, ND-Hi Tech Lab and Etron Technology, appears in 3 co-filed families; IBM's pairing with its UK intellectual-property arm, and Tokyo Electron's pairing with its US holding entity, each appear twice. These look like internal corporate structuring rather than cross-company joint development.
Recent grants show incremental refinement, not new architecture
Intel's EP4109523B1, granted in December 2025, claims a silicide-layer refinement to an already-established buried power rail structure — the kind of narrow, defensible improvement claim that characterises a maturing rather than a nascent claim landscape.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. | 0 | -100% |
| International Business Machines Corporation (IBM) | 0 | -100% |
| Tokyo Electron Limited | 0 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| ND-HI TECH LAB INC | 0 | — |
| Etron Technology, Inc. | 0 | — |
| Intel Corporation | 0 | — |
| Adeia Semiconductor Bonding Technologies Inc. | 0 | — |
Where to take this analysis
The dataset points to a plateaued but not abandoned field. Two directions make sense from here.
Watch for the 2025-2026 publication catch-up
Given the 18-month publication lag, filings from device makers that show zero recent activity may simply not have published yet. Re-checking assignee momentum in six to twelve months will clarify whether the plateau is real or an artefact of the lag.
Explore filing trends in EurekaMap the under-claimed branches against your own roadmap
Thermal modelling, nano-TSV alignment tolerance and wafer-bonding reliability show thinner claim density than the core buried-rail structures. Teams working on these adjacent problems have more room to stake an early, defensible position.
Run a white space search in EurekaCommon questions on backside power delivery patents
A backside power delivery network (backside PDN) moves the power rails and associated vias from the front-side interconnect stack to the back of the wafer, separating power routing from signal routing. This frees up front-side layers for denser signal interconnect and can reduce IR drop by shortening the path from the power source to the transistor. The approach typically depends on wafer bonding and thinning steps plus nano through-silicon vias to connect the backside rail to the front-side transistor layer, which is why those terms cluster together in the patent record.
The dataset shows recent-year momentum tracked across a small group of assignees including Samsung, IBM, Tokyo Electron and TSMC, alongside smaller specialist filers such as ND-Hi Tech Lab and Etron Technology. All of these show zero filings in the latest tracked year, though this likely reflects publication lag rather than an actual pause in R&D. The most-cited individual records in the space, however, trace back further, with several foundational buried-power-rail patents filed by device and foundry companies earlier in the tracked period.
Filing activity rose to a peak of 11 families in 2021 and has not exceeded that level since, with 2022 essentially matching rather than extending it. This pattern is typical of a technology where the core architectural claims — the basic buried power rail structure, the nano-TSV connection scheme, the wafer bonding sequence — were staked out early, leaving later filers to compete on narrower refinement claims rather than broad new territory. It does not mean interest in the technology has declined; foundries continue to pursue backside PDN in production nodes.
Based on the classification and gate analysis of this dataset, several adjacent branches show thinner claim density than the core buried-rail structures: thermal impact modelling specific to buried rails, nano-TSV alignment tolerance control, routing congestion relief algorithms, and wafer bonding interface reliability. These are process- and reliability-adjacent problems rather than core device architecture, and the IPC composition shows most filings sit under core device classifications (H01L, H10W) rather than these more specific process areas.
Patent applications generally publish about 18 months after filing, so any filing count for the most recent one to two years is understated in every dataset, not just this one. A drop-off in 2025-2026 figures should be read as an artefact of pending publications working through the pipeline, not as a genuine collapse in filing activity. The more reliable read comes from years that are at least two years old, which is why the 2021 peak and the 2022 plateau are treated as the meaningful data points here rather than the tail years.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.