Backside power delivery moves the power rail network from the front side of a chip's interconnect stack to its backside, typically by embedding buried power rails in the substrate and connecting them through backside metallization after wafer thinning. This frees front-side routing layers for signal interconnect only, which helps shrink standard-cell height at advanced nodes. The patent evidence in this dataset shows the core mechanic — a buried rail directly contacted by a backside metal layer — is already densely claimed by early filers, so new work tends to focus on the contact, thinning or integration steps around it.

IBM, Samsung, Intel and TSMC are the most prominent assignees tracked in this landscape, alongside research and equipment players such as imec and Tokyo Electron. IBM shows the densest internal co-filing network, coordinating across its US, UK, China and Germany intellectual-property units rather than filing jointly with outside companies. Notably, all of these leading filers show zero filings in the most recent tracked year, which given normal publication lag likely reflects pending applications not yet public rather than an actual stop in R&D.

Filing volume rose from a single family in 2017 to a peak of 122 in 2022, then fell in the following years. That pattern is typical of a technology moving from early demonstration into a period where the foundational structural claims — the buried rail itself and its basic backside contact — get staked out quickly by a handful of filers, after which the pace of genuinely new structural claims slows. It does not mean R&D activity has stopped; publication lag of roughly 18 months means the most recent one to two years of this trend are understated in the public record.

US12568814B2, assigned to International Business Machines Corporation and published 2026-03-03, claims a semiconductor structure where a buried power rail extends below the substrate's backside and is in direct contact with a portion of the first metal layer of the backside power delivery network, with the rail and that metal layer made of the same conductive material. That same-material direct-contact detail is the specific feature to check against: any design routing a buried rail into direct contact with a backside first-metal layer using matching conductive materials sits close to this claim's scope and warrants a closer freedom-to-operate read rather than an assumption of clearance.

Based on IPC composition, the core buried-rail and backside-metallization structures under H01L, H10W and H10D are heavily claimed, while adjacent areas show visibly lower density: memory-specific integration (H10B, 19 families), data-processing co-design (G06F, 7 families), nanotechnology-scale contact approaches (B82Y, 5 families) and power-conversion circuit co-design (H02M, just 2 families) are comparatively open. Nano-TSV contact resistance reduction and wafer-thinning defect control for buried rails are two specific mechanics inside those adjacent areas worth a first-claim search before filing.