Beyond-CMOS Device Patents: Who Leads, Where the Gaps Are 2026
- Concentrated top of field. the top 5 assignees hold 65.7% of all 67 records in scope, and the top 10 hold 86.6% — a long tail of single- and double-filing entrants sits behind them.
- Filing has pulled back sharply. from 5 records in 2021 to 2 in 2024, a 60% drop over that span, after a 2018 peak of 12 — though 2025-26 counts are still filling in due to publication lag.
- Memory and magnetics dominate the claim space. H01L covers 85.1% of records and H10D 28.4%, while narrower classes like H10B (memory device manufacture, 9.0%) and H01F (magnets/inductors, 13.4%) leave visibly thinner coverage.
Filing growth compares 2021 (5 records) with 2024 (2) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 67 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This dataset tracks 67 published patent records filed against post-CMOS device architectures — search terms spanning “post CMOS device,” “emerging logic device” and “Beyond CMOS” combined with core structural claims like transistor structure, wafer substrate, mask layer and process integration. The scope runs from 2015 through the 2026-08-31 cut-off, capturing the period in which university labs and a handful of large semiconductor incumbents began filing seriously on device architectures meant to succeed or supplement bulk CMOS scaling.
Filing offices skew heavily toward the United States (47 of the tracked records), with WIPO PCT filings, EPO and a smaller India presence rounding out the international footprint. That distribution says more about where these applicants file first than about where the technology will ultimately be used.
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Filing trend and technology composition
The filing curve and the IPC breakdown below are drawn from the same 67-record set that anchors every figure on this page.
A 2018 peak followed by a multi-year pullback
Filings ran from 6 in 2017 to a peak of 12 in 2018, then eased. The clearest recent signal is a drop from 5 records in 2021 to 2 in 2024 — a 60% decline over three years. Because publication trails filing by roughly 18 months, 2025 and 2026 counts are not yet complete and should not be read as a continuation of that decline.
H01L and H10D anchor the field
H01L (semiconductor devices) appears on 85.1% of the 67 records, and H10D (semiconductor devices, general) on 28.4% — together confirming that most filings still frame novel devices as variants of conventional semiconductor structures. Narrower classes such as G11C (static & digital memories, 19.4%), B82Y (nanotechnology, 17.9%), H03K (pulse technique & logic circuits, 17.9%) and H10N (other solid-state devices, 17.9%) show where specialised architectures are being claimed, while H10B (memory device manufacture, 9.0%) remains comparatively thin.
Shares are the percentage of the 67 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Beyond-CMOS & Novel Devices Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about beyond-cmos & novel devices patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this landscape
Two-Transistor Floating-Body Dynamic Memory Cell
Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.Filed by University of Florida Research Foundation; among the most-cited records in this dataset with 37 citations.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20150333534A1 | Low Power Nanoelectronics | 62 |
| 2 | US20100329043A1 | Two-Transistor Floating-Body Dynamic Memory Cell | 37 |
| 3 | US20180374962A1 | Two-dimensional electrostrictive field effect transistor (2d-EFET) | 36 |
| 4 | US9979401B2 | Magnetoelectric computational devices | 23 |
| 5 | US20230144206A1 | Packaging architectures for sub-terahertz radio frequency devices | 19 |
| 6 | US10817463B1 | Adiabatic circuits for cold scalable electronics | 15 |
| 7 | US8498140B2 | Two-transistor floating-body dynamic memory cell | 15 |
| 8 | US20100311213A1 | Method of forming an inverted t shaped channel structure for an inverted t channel field effect transistor de… | 10 |
| 9 | US8158484B2 | Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor de… | 10 |
| 10 | US20180248554A1 | Magnetoelectric Computational Devices | 8 |
Citation counts reflect an aggressive-continuation and multi-jurisdiction searched corpus, and they favour older filings by construction — treat them as a signal of influence rather than of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns in this dataset matter more to a filing strategy than the raw counts alone.
The top of the field is narrow
Five assignees hold 65.7% of all 67 records in scope, and the top 10 extend that to 86.6%. That leaves a long tail of single- or double-filing entrants — mostly individual inventors and smaller research foundations — competing for the remainder.
Filing has cooled since 2021
The clean three-year comparison the dataset supports is a drop from 5 records in 2021 to 2 in 2024, a 60% decline. This followed a 2018 peak of 12 records and suggests the initial wave of exploratory filings has slowed even before accounting for publication lag on the most recent years.
Claims still frame devices as semiconductor variants
H01L accounts for 85.1% of records and H10D for 28.4%, meaning most applicants are still anchoring novel-device claims inside conventional semiconductor-device classification rather than filing into dedicated beyond-CMOS categories. Nanotechnology (B82Y, 17.9%) and magnetics (H01F, 13.4%) mark where the departures from that pattern concentrate.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to beyond-cmos & novel devices patent landscape, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Board of Regents, The University of Texas System | NeoTek Ventus Corporation | 2 |
| University of Florida Research Foundation, Inc. | TRIVEDI VISHAL P | 2 |
| University of Florida Research Foundation, Inc. | SADD MICHAEL | 2 |
| University of Florida Research Foundation, Inc. | MATHEW LEO | 2 |
| University of Florida Research Foundation, Inc. | FOSSUM JERRY G | 2 |
| Freescale Semiconductor, Inc. | WILD ANDREAS | 1 |
| Freescale Semiconductor, Inc. | ORLOWSKI MARIUS | 1 |
Only 7 co-assignee pairs appear across the dataset, each linking a university foundation to a corporate or individual co-filer rather than forming a dense collaboration network — most assignees here file alone.
Who is filing, and who has stopped
The assignee ranking is dominated by university research foundations and one large semiconductor incumbent, with recent-year activity flat across the leaders tracked.
A single assignee leads by a wide margin
The top-ranked assignee holds 20 records against a fifth-place figure of 5 and a tenth-place figure of 2 — a steep drop-off that marks this as a leader-and-field pattern rather than a tightly bunched top ten.
Momentum has gone flat at the top
Every one of the six leading assignees tracked for recent-year momentum shows 0 records in the latest year. That is consistent with the broader 2021-to-2024 pullback and does not necessarily mean these organisations have exited the space — it may reflect the publication lag on very recent filings.
Filing is mostly solo, not networked
Just 7 co-assignee pairs exist across the dataset, the strongest linking a university system to a corporate co-filer and, separately, a university foundation to individual named inventors. There is no dense collaboration cluster here — most organisations prosecute independently.
| Assignee | Recent year | YoY |
|---|---|---|
| Board of Regents, The University of Texas System | 0 | — |
| Intel Corporation | 0 | — |
| The Penn State Research Foundation | 0 | — |
| Georgia Tech Research Corporation | 0 | — |
| Freescale Semiconductor, Inc. | 0 | — |
| University of Florida Research Foundation, Inc. | 0 | — |
| ZETTAFLOPS LLC | 0 | — |
| NeoTek Ventus Corporation | 0 | — |
Where to take this next
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, white-space filing, or tracking a named competitor.
Check freedom-to-operate against the cited leaders
The most-cited records in this set, including the floating-body memory cell and the 2D electrostrictive FET filings, sit under dense downstream citation. Any new filing in memory-cell or 2D-material transistor structures should be checked against these specifically before drafting claims.
Run a freedom-to-operate check in EurekaTrack the leader's flat recent-year activity
The top-ranked assignee shows 20 records historically but 0 in the latest tracked year, alongside five other leaders showing the same pattern. Whether this reflects a real pullback or publication lag is worth confirming before assuming the field is open.
Set up assignee monitoring in EurekaScope claims into the thinner IPC branches
H10B and H01F carry noticeably lower record shares than H01L or H10D. A first claim drafted specifically into memory device manufacture or magnetics-integration language may face less prior art density than one framed as a general semiconductor device.
Draft against white space in EurekaFrequently asked questions
This landscape scopes records that combine post-CMOS or emerging-logic-device language with concrete structural claims such as transistor structure, wafer substrate, mask layer, device structure or process integration. That combination excludes purely conceptual or materials-science publications that never reach device-structure claim language. The 67 records in scope span 2015 through the 2026 cut-off, drawing filings from US, WIPO, EPO, Indian and other offices.
The ranking returned for this dataset covers 27 companies, led by a single assignee with 20 records against a fifth-place figure of 5 and a tenth-place figure of 2 — a clear leader-and-field structure rather than a tightly bunched group. University research foundations and one large semiconductor incumbent make up most of the top of the ranking. Behind that top group sits a long tail of single- or double-filing entrants, including individual inventors.
Filing peaked at 12 records in 2018 and has since pulled back, with the cleanest recent comparison showing a drop from 5 records in 2021 to 2 in 2024 — a 60% decline over that span. Because publication lags filing by roughly 18 months, the 2025 and 2026 figures in any dataset like this are still incomplete and should not be read as confirming a continued decline. The honest read is a slowdown through 2024, with the most recent trend still unresolved.
H01L (semiconductor devices) appears on 85.1% of the 67 records and H10D (semiconductor devices, general) on 28.4%, meaning the large majority of filings still frame beyond-CMOS work inside conventional semiconductor-device classification. Memory-specific classes like G11C (19.4%) and H10B (9.0%), along with nanotechnology (B82Y, 17.9%) and magnetics (H01F, 13.4%), mark where more specialised architectures are being claimed. Because records can carry multiple IPC codes, these shares add up to more than 100% and should not be summed.
The thinner IPC branches relative to the H01L/H10D core — memory device manufacture (H10B, 9.0%) and magnetics/inductor integration (H01F, 13.4%) — show visibly lower filing density than the dominant classes. Specific device families such as magnetoelectric switching, 2D-material electrostrictive transistors and sub-terahertz RF packaging architectures also show fewer records relative to their citation influence, suggesting room for narrowly drafted claims. Any white-space filing should still be checked against the most-cited records in the relevant class before drafting.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.