Buried Power Rail IR Drop at 2nm — PatSnap Eureka
Buried Power Rail Integration for IR Drop Reduction at 2nm
At sub-3nm standard cell heights, conventional M1/M2 power straps are geometrically unviable. Buried power rail (BPR) technology repositions VDD/VSS conductors below the active device plane — enabling parallel-path shunting, upsized cross-sections, and placement-aware current normalization to eliminate IR drop hotspots.
How Buried Power Rails Reduce Effective Rail Resistance
At the heart of BPR technology is the repositioning of VDD and VSS conductors from front-end-of-line (FEOL) metal layers into trenches carved within the device layer itself. As described in Intel Corporation's 2023 patent, the BPR resides within the device layer neighboring the drain structure, with its uppermost surface below the uppermost surface of the drain. A top-side power rail sits vertically above the BPR, connected to it via a conductive structure.
Intel explicitly articulates the resistance-reduction mechanism: "the buried power rail acts as a shunt for the top-side power rail… Since the buried power rail and top-side power rail are effectively infinitely long in a logic block relative to a single transistor or single logic cell, the resistance of the top-side power rail in parallel [with the BPR] is reduced." This parallel-path shunting directly lowers the effective rail resistance, which is the primary driver of static and dynamic IR drop at high current densities.
Samsung Electronics takes a process-centric approach, describing formation of BPRs within power rail trenches in a dielectric layer on a first semiconductor substrate, followed by wafer bonding of a donor wafer carrying the active device layer. This fabrication flow enables BPR widths to be set lithographically during the substrate preparation stage, decoupled from the standard cell layout pitch constraints that govern front-side metal. Learn more about patent landscape analysis for semiconductor processes on PatSnap.
The geometric constraint problem at tight cell-to-cell pitches — a critical concern at 2nm where adjacent standard cells may share boundary edges — is addressed by IBM's dual-BPR stack: a first BPR with a larger critical dimension (CD) contacts a second BPR with a smaller CD. This stacked geometry allows the effective cross-sectional area of the power conductor to exceed what would be possible through a single trench patterned within the tight cell boundary.
BPR Innovation by Assignee and Technical Focus
Distribution of buried power rail patent families across major semiconductor organizations at sub-3nm nodes, derived from PatSnap Eureka analysis of 15+ directly relevant patent families.
BPR Patent Families by Assignee
ARM, NVIDIA, and Intel lead BPR patent activity at advanced nodes, with ARM holding 3 active US patent families covering bitcell and dual-function buried signal routing.
Dynamic IR Drop Suppression: Single vs. Stacked BPR
Backside buried metal PDNs with distributed capacitance suppress dynamic IR drops by 10% (single-chip) and 59% (four-chip stack) in a 3.9M-gate crypto core at 30 MHz (Kobe University, 2021).
Upsizing BPR Width Beyond Inter-Cell Spacing
IR drop is inversely proportional to rail cross-sectional area. Four complementary strategies from Synopsys, Qualcomm, AMD, and GlobalFoundries address this from different angles — from spatial relocation to aspect ratio control and variable density routing.
BPR Width Greater Than Vertical Space Width
Synopsys explicitly claims an integrated circuit structure where the upsized BPR has a width greater than the width of the vertical space separating adjacent component-bearing structures. The contiguous cavity formed adjacent to the vertical space accommodates a wider conductor without displacing active device regions. By increasing cross-sectional area beyond the inter-cell spacing, the rail resistance per unit length drops proportionally, reducing the IR voltage drop experienced by transistor sources connected to the BPR.
Width > inter-cell gap → resistance ↓High-Aspect-Ratio Voltage Rails (H/W > 1.0)
Qualcomm's invention provides first and second high-aspect-ratio voltage rails with height-to-width ratio greater than 1.0, where the height of each rail exceeds its width. The increased height allows a larger cross-sectional area within a constrained lateral footprint — directly limiting resistance and the corresponding IR drop. This principle is architecturally equivalent to BPR upsizing but implemented via aspect ratio control rather than spatial relocation below the device layer.
H:W > 1.0 → larger cross-sectionDual-Height Cells with Reduced CPP Power Posts
AMD's method employs dual-height standard cells at half the width of single-height cells, placing power posts with 1 contacted gate poly pitch (CPP) to align power rails across cell rows. By increasing the number of power delivery contacts per unit length of the power rail, the effective via resistance is reduced, further lowering IR drop without requiring changes to the back-end metal stack. This cell-architecture-level approach is complementary to process-level BPR strategies.
More contacts per rail length → via R ↓Variable Power Rail Density via Current-Aware Routing
GlobalFoundries' variable power rail design creates standard cells with M2 power rails, then computes power rail current density after routing. Cells with current density below a predetermined threshold are replaced with functionally equivalent cells lacking M2 rails. The design iterates until convergence. This selective de-population of over-provisioned rails restores routing resources in low-activity regions, while high-current zones retain thicker rail infrastructure — a variable-density philosophy that informs modern BPR placement algorithms.
Current-density-aware rail provisioningFront-Side Augmentation, Jumper Connections & Backside PDNs
Before and alongside full BPR adoption, TSMC, Samsung, ARM, and Kobe University developed complementary multi-layer and backside power delivery techniques that remain relevant at 2nm.
| Organization | Technique | IR Drop Mechanism | Year |
|---|---|---|---|
| TSMC | Jumper connections between vertically separated power/ground rails | Creates additional parallel current paths, reduces rail impedance, distributes current uniformly — mitigates both IR drop and electromigration | 2017 |
| Samsung | Dual-metal-layer routing: timing-critical cells powered from lower-resistance second metal layer | Routes high-priority cells to lower-resistance rails, reducing peak noise and IR drop on most timing-sensitive paths | 2020 |
| ARM | Dual-function buried supply rail: backside power network + signal path for critical nets | Reduces front-side routing congestion while providing low-resistance power delivery — synergistic benefit of buried-layer paradigm | 2022 |
| ARM | Bitcell buried ground rail: ROM cells connected between bitlines and buried VSS rail via backside IVs | Reduces length of ground current path, directly reducing resistive voltage drop along VSS rail | 2022 |
| Kobe University | Backside buried metal PDN with distributed capacitance over full-chip backside area | Suppresses dynamic IR drops by 10% (single-chip) and 59% (four-chip stack) in 3.9M-gate crypto core at 30 MHz | 2021 |
| IBM | Power staple avoidance: shift transistor gates to prevent pin-to-staple alignment during routing | Reduces via count in congested areas while maintaining current delivery, managing resistance along local rail segments | 2025 |
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Placement-Aware IR Drop Mitigation at the Algorithm Level
BPR effectiveness at 2nm depends not only on physical rail geometry but on intelligent standard cell placement that prevents current density spikes along rails. NVIDIA and IBM lead the EDA-side innovation.
NVIDIA: Rail Power Density Aware Placement (2023–2025)
NVIDIA's methodology reorganizes cell placement within bounding box regions before fabrication. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. IR drop is mitigated because distributing current consumption between supply rails reduces current spikes and IR drops. The reorganization achieves minimal timing impact. This EDA-level approach is complementary to BPR geometry: even a low-resistance buried rail will suffer localized IR drop if high-switching-activity cells are clustered at a single rail segment.
IBM: Power Staple Avoidance for Via Reduction (2025)
IBM's 2025 technique shifts transistor gates within rows to avoid alignment of cell pins and power staples during routing. By preventing pin-to-staple alignment, the methodology reduces via count in congested areas while maintaining adequate current delivery, directly managing resistance along local rail segments. This technique is particularly relevant at 2nm where the number of available routing tracks per cell is severely limited. For further context on international patent filings in this space, WIPO data confirms accelerating BPR-related WO applications from 2022 onward.
Who Owns the BPR Innovation Landscape at 2nm?
A small set of vertically integrated IDMs and major IP licensors dominate BPR patent activity. Understanding their claim boundaries is essential for R&D teams targeting 2nm and below. Explore the full PatSnap customer case studies to see how IP teams navigate this landscape.
Core BPR Structural Architecture
Intel leads in core BPR structural patents, defining the buried-rail-plus-top-rail shunting architecture and the trench contact via (TVB) self-alignment methodology. Two 2023 WO/US patent families establish the foundational claim that the BPR acts as a shunt for the top-side power rail, with resistance reduced in parallel.
2 patent families · 2023Tight Cell-to-Cell Spacing Integration
IBM advances BPR integration under tight cell-to-cell spacing constraints via dual-BPR stacking, as seen in 2023 WO and US filings. IBM also holds the 2025 power staple avoidance patent for routing via reduction at congested cell boundaries.
2 patent families · 2023–2025Dual-Function Buried Signal Routing
ARM extends BPR architecture to memory bitcells and dual-function buried signal routing, with three 2022 active US patent families. ARM's buried metal technique enables at least one buried supply rail to serve as a backside signal path for critical signal nets — providing architectural justification beyond IR drop alone for BPR adoption.
3 patent families · 2022EDA-Side Placement Normalization
NVIDIA owns the EDA-side of the BPR problem, with a patent family spanning 2023–2025 on rail-power-density-aware placement. Cell reorganization within bounding boxes normalizes temporal and spatial power density, preventing IR hotspots even on geometrically optimized buried rails. The PatSnap platform tracks all three NVIDIA continuations.
3 patent families · 2023–2025Four Interconnected BPR Strategies at 2nm
The dominant technical approaches converge across four interconnected strategies that must be co-designed simultaneously for effective IR drop reduction at the 2nm node.
BPR Co-Design Strategy Flow: Process → Cell → EDA → Verification
All four strategies must be implemented simultaneously. A low-resistance buried rail geometry is ineffective without placement-aware EDA; upsized cross-sections require process integration advances to achieve.
Buried Power Rail IR Drop at 2nm — key questions answered
A buried power rail repositions VDD and VSS conductors from front-end-of-line metal layers into trenches carved within the device layer itself. The BPR resides within the device layer neighboring the drain structure. A top-side power rail sits vertically above the BPR, connected via a conductive structure. The BPR acts as a shunt for the top-side power rail — since both rails are effectively infinitely long relative to a single transistor, the resistance of the top-side rail in parallel with the BPR is reduced, directly lowering static and dynamic IR drop at high current densities.
IBM's approach introduces a dual-BPR stack: a first BPR disposed through etch stop layers with a larger critical dimension (CD), and a second BPR in direct contact with the first BPR with a smaller CD. The bottom surface of the first BPR contacts a via-to-BPR (VBPR) contact connecting source/drain regions. This stacked geometry allows the effective cross-sectional area of the power conductor to exceed what would be possible through a single trench patterned within the tight cell boundary, directly reducing rail resistance and IR drop.
BPR upsizing refers to forming a buried power rail with a width greater than the width of the vertical space separating adjacent component-bearing structures. The contiguous cavity formed adjacent to the vertical space accommodates a wider conductor without displacing active device regions. By increasing cross-sectional area beyond the inter-cell spacing, the rail resistance per unit length drops proportionally, reducing the IR voltage drop experienced by transistor sources connected to the BPR. Synopsys explicitly claims this in a 2025 US patent.
Research from Kobe University (2021) demonstrated that backside buried metal power delivery networks embedding distributed capacitance over a full-chip backside area suppress dynamic IR drops by 10% in single-chip and 59% in four-chip stack configurations during operation of a 3.9M-gate crypto core at 30 MHz.
NVIDIA's methodology reorganizes cell placement within bounding box regions before fabrication. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. IR drop is mitigated because distributing current consumption between supply rails reduces current spikes and IR drops. This EDA-level approach is complementary to BPR geometry: even a low-resistance buried rail will suffer localized IR drop if high-switching-activity cells are clustered at a single rail segment.
Yes. ARM Limited describes a device where at least one buried supply rail serves a dual function as a backside signal path for critical signal nets. This architectural innovation allows the buried layer to reduce front-side routing congestion for signal wires while simultaneously providing low-resistance power delivery — a synergistic benefit unique to the buried-layer paradigm.
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References
- Integrated circuit structure with buried power rail — Intel Corporation, 2023 (Patent ID: ef41c3bb)
- Integrated circuit structure with buried power rail — Intel Corporation, 2023 (Patent ID: 2ae82049)
- Buried power rail at tight cell-to-cell space — International Business Machines Corporation, 2023 (Patent ID: edc3e27e)
- Buried power rail at tight cell-to-cell space — International Business Machines Corporation, 2023 (Patent ID: 7733b928)
- Integrated circuit with buried power rail and methods of manufacturing the same — Samsung Electronics Co., Ltd., 2020
- Upsizing buried power rails to reduce power supply resistance and boost cell density scaling — Synopsys, Inc., 2025
- Rail power density aware standard cell placement for integrated circuits — NVIDIA Corporation, 2023
- Rail power density aware standard cell placement for integrated circuits — NVIDIA Corporation, 2024 (continuation 1)
- Rail power density aware standard cell placement for integrated circuits — NVIDIA Corporation, 2024 (continuation 2)
- Standard cell circuits employing high aspect ratio voltage rails for reduced resistance — Qualcomm Incorporated, 2024
- Standard cell circuits employing high aspect ratio voltage rails for reduced resistance — Qualcomm Incorporated, 2019
- Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells — Advanced Micro Devices, Inc., 2023
- Buried Metal Technique for Critical Signal Nets — ARM Limited, 2022 (Patent ID: 1afe38ec)
- Buried metal technique for critical signal nets — ARM Limited, 2022 (Patent ID: b15ec552)
- Bitcell architecture with buried ground rail — ARM Limited, 2022
- Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects — Taiwan Semiconductor Manufacturing Co., Ltd., 2017
- Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects — Taiwan Semiconductor Manufacturing Co., Ltd., 2014
- Variable power rail design — GlobalFoundries Inc., 2014
- Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell — Samsung Electronics Co., Ltd., 2020
- Power staple avoidance for routing via reduction — International Business Machines Corporation, 2025
- 3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance — Kobe University, 2021
- IEEE — Institute of Electrical and Electronics Engineers — Semiconductor process and EDA standards body
- WIPO — World Intellectual Property Organization — International patent filing data and PCT applications
- Semiconductor Industry Association (SIA) — Industry roadmap and process node definitions
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
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