Chalcogenide OTS Selector Patents 2026 — PatSnap Eureka
Chalcogenide OTS Selector Technology Landscape 2026
Chalcogenide Ovonic Threshold Switch (OTS) selectors have become the dominant selector technology for high-density cross-point memory. This landscape analyzes 70+ retrieved patent and literature records spanning 1968 to 2026.
OTS Selectors: From Amorphous Films to Storage-Class Memory
Ovonic Threshold Switching exploits the electrical bistability of amorphous chalcogenide thin films based on group-16 elements (S, Se, Te) combined with Ge, Si, As, Sb, and In. In the pristine amorphous state, OTS films are highly resistive (off-state, >10 MΩ). When applied voltage exceeds threshold voltage (V_th), the device transitions abruptly to a low-resistance on-state through purely electronic conduction involving sub-gap trap states and lone-pair electron liberation.
The switching phenomenon was first described by S.R. Ovshinsky at Energy Conversion Devices (ECD) in 1968. Early filings established chalcogenide bistability and reduced first-fire voltage as primary engineering objectives. Ovonyx, Inc. extended this to active-matrix LCD pixel isolation as early as 1997–1998, demonstrating the breadth of the original vision.
The most technically active cluster — 2021–2026 — reflects maturation into advanced material systems, new selector-only memory (SOM) architectures, and novel application domains including DRAM replacement, vertical 3D integration, and RF switching. Samsung Electronics filed two vertical-memory OTS patents in February–March 2026, while imec vzw and KU Leuven filed arsenic-free composition families in 2024.
In this dataset, filing activity accelerated sharply post-2020, with 30+ records in the 2021–2026 window compared to ~18 records in 2011–2020. The landscape is moderately concentrated at the foundational IP layer in retrieved records, with Ovonyx Memory Technology (~10 records) and STMicroelectronics (~7 records) as the top two assignees by volume.
Decadal Filing Acceleration and Technology Cluster Distribution
Filing activity in this dataset reveals a clear acceleration after 2020, with 30+ records in 2021–2026 compared to ~18 in 2011–2020 and ~14 in 2000–2010. Four primary technology clusters account for the bulk of innovation signals across the retrieved records.
OTS Patent Records by Decade (Dataset Snapshot)
In this dataset, post-2020 filings account for the largest single-period volume (~30+ records), surpassing all prior decades and indicating active commercial scaling of OTS technology.
↗ Click bars to exploreOTS Innovation by Technology Cluster (Dataset Snapshot)
In this dataset, device architecture and electrode engineering records alongside multi-element alloy composition filings represent the two largest clusters, with arsenic-free compositions and novel application domains emerging as active growth areas post-2022.
↗ Click bars to exploreKey OTS Selector Application Domains Across the Dataset
OTS selectors have been applied across seven distinct domains in retrieved records, ranging from the primary commercial target of cross-point non-volatile memory to emerging uses in DRAM replacement, RF switching, neuromorphic computing, and spaceborne radiation-hardened systems.
Cross-Point Storage-Class Memory
The primary commercial target across retrieved records, pairing OTS with PCM (PCRAM) in 1S1R cell stacks to eliminate sneak-path current in large cross-point arrays. Multiple Ovonyx Memory Technology patents (US, 2007–2015) define the foundational 1S1R architecture. TSMC’s GeCTe-based OTS (US, 2022, 2025) and IBM’s S-doped AsSeGeSi selectors (US, 2022) explicitly target storage-class memory cross-point arrays.
Non-Volatile MemoryVertical 3D Non-Volatile Memory
Samsung Electronics’ February–March 2026 US, EP, and CN filings propose Ge-Sb-Se-In quaternary OTS materials (Ge: 10–40 at%, Sb: 10–40 at%, Se: 20–80 at%, doped with In) in vertical array structures analogous to 3D NAND. SanDisk Technologies filed on a vertical channel OTS with an outer resistive heating layer to thermally modulate V_th (US/WO, 2020–2021), establishing earlier prior art in this architecture domain.
3D Memory IntegrationDRAM Replacement 1S1C Architecture
Huazhong University of Science and Technology (US, 2025) proposes a conductive-bridge threshold switch (CBTS) variant with extremely low off-state leakage in series with a capacitor (1S1C cell) to extend capacitor retention time and reduce refresh frequency, targeting DRAM replacement. This application exploits OTS two-terminal scalability to address the fundamental refresh-power cost of conventional DRAM.
Emerging MemoryRF Switches and Radiation-Hardened Systems
NASA demonstrated chalcogenide nanoionic RF switches for space applications using Ag or Cu photo-dissolution in chalcogenide glass (US, 2013). Shenzhen University’s 2026 CN patent extends OTS-based RF switches to wireless communication using doped amorphous chalcogenide nanoscale thin films with low drive voltage. Gula Consulting LLC (US, 2005, 2008) covers radiation-hardened chalcogenide C-RAM for satellite FPGAs exploiting OTS material insensitivity to total ionizing dose.
RF & Space ApplicationsKey Patent Assignees in OTS Selector Technology (Retrieved Records)
In this dataset, Ovonyx Memory Technology, LLC holds the highest filing volume at approximately 10 records covering foundational OTS-PCM integration IP, while STMicroelectronics accounts for approximately 7 records in retrieved records focused on the TSLAGS multi-element alloy and process innovation. Samsung Electronics represents the most recent high-activity assignee with 2026 filings on vertical memory and SOM architectures.
Top OTS Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreOvonyx Memory Technology, LLC
In this dataset, Ovonyx Memory Technology holds the highest filing volume at approximately 10 records spanning US jurisdictions from 2007 to 2015. Patents cover OTS-PCM integration methodologies including shared chalcogenide layers, intermediate electrode formation in pores, optical OTS variants, and 1S1R cross-point cell architectures. The IP portfolio is described as largely inactive or expired in retrieved records.
United StatesSTMicroelectronics S.R.L. / SRL
STMicroelectronics accounts for approximately 7 records in retrieved records across US and EP jurisdictions, filed from 2007 to 2014. Key patents cover the proprietary TSLAGS multi-element alloy (Te-S alloy of La, Ge, Si with As 9–39 at%, Ge 10–40 at%, Si 5–18 at%), carbon passivation layer integration, and angled ion implantation for edge-resistance enhancement. These filings represent the first systematic multi-element alloying approach for production-grade OTS in this dataset.
Italy / Europe (US, EP)Six Emerging Directions in OTS Selector Innovation (2022–2026)
Records filed in 2022–2026 in this dataset reveal six directional signals spanning vertical integration architectures, selector-only memory paradigms, arsenic-free material systems, novel electrode interfaces, RF switching applications, and process-level microwave annealing innovations.
Vertical OTS Integration for Ultra-High Density
Samsung’s 2026 US, EP, and CN filings address OTS materials in vertical memory device structures analogous to 3D NAND cell architectures. The Ge-Sb-Se-In quaternary material (Ge: 10–40 at%, Sb: 10–40 at%, Se: 20–80 at%, doped with In) is specifically optimized for vertical stack integration. This represents the most significant near-term architectural shift identified in this dataset.
Selector-Only Memory (SOM) Architectures
Samsung’s 2026 EP filing introduces selector-only memory (SOM), where a single OTS element with voltage-polarity-dependent dual threshold voltages serves simultaneously as selector and storage medium, eliminating the separate memory element entirely. This shifts the paradigm from 1S1R toward 1S0R architectures, reducing cell stack complexity by approximately half. The concept is also closely related to neuromorphic computing applications where OTS-like nonlinear elements model synaptic behavior.
Multi-Element Alloy vs. Arsenic-Free Binary/Ternary OTS Compositions
Click any row to explore further.
| Dimension | Multi-Element Alloy (e.g. TSLAGS, SiGeSeAs) | As-Free Binary/Ternary (e.g. Si-S, Si-Te-P, GeS) |
|---|---|---|
| Representative Assignees | STMicroelectronics, IBM, Macronix, Intel | imec vzw, KU Leuven, Korea Inst. of Science & Technology, POSTECH |
| Composition Complexity | 5–6 elements (As, Ge, Si, Te, S/Se, N optional); multi-degree-of-freedom tuning | 2–3 elements; simplified stoichiometry, ternary purity constraint ≥0.90 mole fraction core |
| Environmental Compliance | Contains arsenic (As); subject to REACH regulation scrutiny in fab environments | Arsenic-free by design; driven explicitly by REACH regulation and fab safety concerns |
| Key Performance Metrics | IBM: oxidation suppressed with 1–10 at% chalcogen passivation; STMicroelectronics: V_th/bandgap independently tunable via S/Se and S/Te ratios | GeS: drive current density 34 MA/cm², ~10⁶ nonlinearity; Ag-Ga₂Te₃: selectivity 10⁸, endurance 10⁹ cycles, off-state current <100 fA |
| Filing Period in Dataset | 2007–2022 (peak 2010–2014 for TSLAGS); IBM 2021–2022 | 2014–2026 (peak 2024 for imec/KU Leuven As-free families) |
| Integration Target | Back-end-of-line CMOS (IBM), production-grade PCM arrays (STMicroelectronics), CMOS foundry (TSMC GeCTe) | REACH-compliant fabs, next-generation cross-point arrays; Si-S and Si-Te-P spaces described as underexplored in this dataset |
| IP Status (Dataset) | Active (IBM, TSMC 2022–2025); STMicroelectronics TSLAGS largely established; Intel filings (2007–2009) older | Active and recent; imec/KU Leuven 2024 EP and US filings pending or recently granted |
Frequently Asked Questions: Chalcogenide OTS Selector Patents & Technology
An OTS selector is a two-terminal electronic switching device that exploits the electrical bistability of amorphous chalcogenide thin films. In the pristine amorphous state, the film is highly resistive (off-state, >10 MΩ). When applied voltage exceeds the threshold voltage (V_th), it transitions abruptly to a low-resistance on-state through purely electronic conduction involving sub-gap trap states and lone-pair electron liberation — without a permanent phase change. Upon removal of the bias below the holding voltage (V_H), it reverts to the high-resistance state.
The switching phenomenon was first described by S.R. Ovshinsky at Energy Conversion Devices (ECD) in 1968. Early patent filings from ECD, including the ‘Switch with improved threshold voltage’ family in CA and EP jurisdictions (1992–1996), established chalcogenide bistability and reduced first-fire voltage as primary engineering objectives. Ovonyx, Inc. (a successor entity) filed a thin-film structure patent addressing edge-conductivity problems in 1993.
TSLAGS (Te-S alloy of La, Ge, Si) is a proprietary multi-element OTS chalcogenide alloy developed by STMicroelectronics. It incorporates As (9–39 at%), Ge (10–40 at%), Si (5–18 at%), N (0–10 at%), plus a ternary S-Se-Te alloy with controlled S/Se (0.25–4) and S/Te (0.11–1) ratios. STMicroelectronics filed the multi-jurisdiction TSLAGS series (US, EP) from 2010 to 2014, representing the first systematic multi-element alloying approach for production-grade OTS in retrieved records.
imec vzw and KU Leuven have filed 2024 EP and US patents on Si-S, Si-Te-S, and Si-Te-P OTS compositions that eliminate arsenic entirely. The S-containing OTS specifies at least 0.90 mole fraction of a Si/Ge/Sn + S core with at most 0.10 mole fraction of other elements. The Te-containing OTS specifies Si (0.20–0.70) + Te (0.05–0.60) + S and/or P. Ab initio screening across ternary composition space was used to identify thermally stable amorphous candidates. These are driven by REACH regulation and fab safety concerns.
Samsung’s 2026 EP filing introduces selector-only memory (SOM), where a single OTS element with voltage-polarity-dependent dual threshold voltages serves simultaneously as selector and storage medium, eliminating the separate memory element entirely. This shifts the paradigm from 1S1R (one selector, one resistor/memory) toward 1S0R architectures, reducing cell stack complexity by approximately half. Samsung’s 2026 US and CN filings also propose Ge-Sb-Se-In quaternary materials in vertical array structures for high-density integration.
Retrieved records document several non-memory applications: Ovonyx, Inc. (US, 1997–1998) patented OTS for active-matrix LCD pixel isolation using off-state resistance >10¹⁰ Ω. NASA demonstrated chalcogenide nanoionic RF switches for space applications (US, 2013), and Shenzhen University filed on OTS-based RF switches for wireless communication (CN, 2026). Gula Consulting LLC (US, 2005, 2008) covers radiation-hardened chalcogenide C-RAM for satellite FPGAs. Huazhong University of Science and Technology (US, 2025) proposes a conductive-bridge threshold switch for DRAM replacement.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.