Chiplet Architecture for High-Performance Processors — PatSnap Eureka
How Chiplet Architecture Is Transforming High-Performance Processor Design
Monolithic SoC design is hitting hard physical and economic limits. Chiplet-based heterogeneous integration — disaggregating dies across optimal process nodes and assembling them via advanced packaging — is now the dominant path to scalable compute performance. Explore the patents, players, and engineering realities driving this shift.
Why Monolithic SoC Design Is Economically Untenable at Advanced Nodes
For decades, the dominant processor design philosophy was integration: pack more transistors, more IP cores, and more memory controllers onto a single monolithic die. However, as the National University of Defense Technology's 2020 analysis — surfaced via PatSnap Eureka — explains, "as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets." The failure of both Moore's Law and Dennard scaling has made continued monolithic integration economically and technically unsustainable.
A critical structural problem is manufacturing yield. Intel's active patent on SoC disaggregation states directly: "Building larger and larger silicon dies is challenging for a variety of reasons. As silicon dies become larger, manufacturing yields become smaller and process technology requirements for different components may diverge." Different functional blocks — logic, memory, analog I/O — have different optimal process nodes, and forcing them onto a single die means compromising performance or paying a significant cost premium.
Tsinghua University's quantitative cost model (2022) demonstrates that multi-chip integration "can reduce the total cost of the VLSI system through appropriate multi-chiplet architecture" — specifically through yield improvement, chiplet and package reuse, and process heterogeneity. The global semiconductor industry has converged on chiplet disaggregation as the structural answer. As Nanjing University's 2024 patent notes, "advanced manufacturing process costs rise exponentially" and "storage and I/O sections occupy the majority of chip area, so as the chip process advances, the CPU performance gains are minimal." Chiplet disaggregation allows each block to be independently right-sized to its ideal process node, a principle now codified across more than a dozen active patents tracked by PatSnap.
Packaging, Interconnect, and Memory Integration in Chiplet Systems
The physical realization of chiplet-based processors depends critically on advanced packaging technologies and high-bandwidth die-to-die interconnects — the primary determinants of whether a disaggregated system can match a monolithic counterpart.
2.5D, 3D, and Fan-Out Packaging
Shanghai Sharetek Technology's 2022 research documents how "Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3D, and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the storage wall problem." The storage wall — the performance gap between processor speed and memory bandwidth — is one of the primary motivations for chiplet-based memory integration.
Alleviates the storage wallSilicon-Photonic Interposer Networks
Colorado State University's 2022 paper on ReSiPI — a reconfigurable silicon-photonic 2.5D interposer network — notes that "connecting the chiplets through an electronic interposer imposes a high traffic load on the interposer network." Their solution uses phase-change materials and dynamic photonic gateways to reduce power consumption while sustaining high inter-chiplet bandwidth as chiplet counts scale up.
Phase-change material gatewaysOperand-Tracking Synchronization (WARF)
Wisconsin Alumni Research Foundation's 2024–2025 patents on Cache Synchronization for Chiplet Accelerators describe architectures that "provide for a reduction in cache synchronization operations by tracking a relationship between chiplet execution kernels and array operands to elide synchronization when particular arrays are not in use in the caches of other chiplets." This is tailored to inter-chiplet latency realities where unnecessary synchronization costs are far higher than within a monolithic die.
Elide unnecessary sync opsIntel's Interchangeable Chiplet Slots
Intel's 2023 patent on late-bind SKU fungibility describes a modular parallel processor with "an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots." The plurality of chiplets is "interchangeable during assembly" — enabling a single base die to serve multiple product SKUs and dramatically reducing design complexity and time-to-market for entire processor families.
Single base die, multiple SKUsChiplet Architecture: Technical Focus Areas and Key Patent Activity
Analysis of more than a dozen patents and academic papers reveals where the chiplet innovation frontier is concentrated — from SoC disaggregation to AI acceleration and fault-tolerant self-organization.
Chiplet Technical Focus Areas Across Patent Dataset
SoC disaggregation and memory integration dominate the dataset, followed closely by cache coherency and AI acceleration innovation.
Patent Assignee Distribution in Chiplet Dataset
Intel leads with the highest concentration of active and pending patents, followed by Chinese research institutions and companies at 28%.
From AI Acceleration to Fault-Tolerant Embedded Systems
Chiplet architecture's compositional flexibility makes it applicable across a wide range of high-performance computing domains, each with distinct requirements for compute types, memory access patterns, and reliability.
AI and Deep Learning Acceleration
Robert Bosch's 2026 pending patent on chiplet architecture for a technical system explicitly incorporates "a hardware accelerator for applications using artificial intelligence" as one of the core chiplets — alongside a CPU, GPU, system management control unit, and working memory. This reflects industry recognition that AI inference and training impose compute patterns distinct from general-purpose processing, requiring a dedicated accelerator chiplet mixed into the system.
Dynamic Resource Scheduling for Accelerators
Zhongcheng Hualong's 2023 hardware acceleration patent uses a resource manager to "intelligently schedule sub-tasks to corresponding hardware accelerator chiplets, and monitor processing status and the status of each hardware accelerator chiplet, dynamically adjusting the number of different types of chiplet accelerators needed." The result is real-time reallocation across diverse concurrent workloads — directly addressing the underutilization of fixed-function monolithic accelerators.
Most Active Chiplet Architecture Patent Assignees
Based on the analyzed dataset, these organizations are the most active and impactful contributors to chiplet architecture for high-performance processors — spanning the US, EU, and China.
| Assignee | Innovation Focus | Representative Patent | Jurisdiction | Status |
|---|---|---|---|---|
| Intel Corporation | SoC disaggregation, late-bind SKU fungibility, memory chiplet integration | Disaggregation of SoC Architecture (multiple) | US, SG | Active |
| Advanced Micro Devices (AMD) | Runtime performance optimization across heterogeneous chiplet arrays | Using chiplet-level performance information for configuring chiplets | WO | Active |
| Wisconsin Alumni Research Foundation | Cache coherency and synchronization for chiplet accelerators | Cache Synchronization for Chiplet Accelerators | US | Active |
| Robert Bosch GmbH | Embedded and safety-critical chiplet systems with AI accelerator integration | Chiplet architecture for a technical system | DE | Pending |
Track Chiplet IP Across All Jurisdictions in Real Time
Monitor Intel, AMD, WARF, Bosch, and Chinese filers as new patents publish — with PatSnap Analytics.
What the Chiplet Patent Landscape Tells Semiconductor Teams
Monolithic SoC design is economically untenable at advanced nodes. Rising fabrication costs, yield losses from large die sizes, and divergent process requirements across functional blocks make disaggregation into chiplets a structural necessity — as established by the National University of Defense Technology's landmark 2020 analysis, now accessible via PatSnap Eureka.
Intel's SoC disaggregation patents define the foundational chiplet assembly model, enabling GPUs and parallel processors to be "composed from diverse silicon chiplets that are separately manufactured." Late-bind SKU fungibility — where chiplets are "interchangeable during assembly" — allows a single base die to serve multiple product tiers, reducing product family design cost significantly. For teams monitoring competitive IP, PatSnap's domain solutions provide structured access to these filings.
Runtime chiplet management is an emerging differentiator. AMD's 2023 patent demonstrates that selecting and configuring chiplets dynamically based on measured per-chiplet performance characteristics enables system-level optimization not possible in monolithic designs. Meanwhile, WIPO's global patent filing data confirms that chiplet innovation is accelerating across all major jurisdictions — including the US, EP, DE, SG, CN, and WO. The convergence of hardware modularity with software-defined management — from AMD's runtime controller to LTU Licens AB's microservice abstraction — marks the leading edge of chiplet architecture innovation for high-performance processor development.
Chiplet Architecture for High-Performance Processors — key questions answered
As process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on chiplets. Building larger and larger silicon dies is challenging because manufacturing yields become smaller and process technology requirements for different components may diverge. Chiplet disaggregation allows each block to be independently right-sized to its ideal process node.
Intel's chiplet architecture for late bind SKU fungibility describes a modular parallel processor with an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots onto which chiplets are vertically stacked. The plurality of chiplets is interchangeable during assembly and includes a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. This late-bind approach enables a single base die design to serve multiple product SKUs, dramatically reducing design complexity and time-to-market for product families.
Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3D, and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the storage wall problem. Intel's packaged device patents describe techniques for providing at a packaged device an integrated circuit chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip — enabling tight processor-memory co-packaging that short-circuits off-package memory bandwidth bottlenecks.
Wisconsin Alumni Research Foundation's patents on Cache Synchronization for Chiplet Accelerators describe architectures that provide for a reduction in cache synchronization operations by tracking a relationship between chiplet execution kernels and array operands to elide synchronization when particular arrays are not in use in the caches of other chiplets. This approach is tailored to the latency and bandwidth realities of inter-chiplet communication, where the cost of unnecessary synchronization is considerably higher than within a monolithic die.
Robert Bosch's patent on chiplet architecture for a technical system explicitly incorporates a hardware accelerator for applications using artificial intelligence as one of the core chiplets within a multi-functional architecture that also includes a CPU, GPU, system management control unit, and working memory. Zhongcheng Hualong's hardware acceleration patent uses a resource manager to intelligently schedule sub-tasks to corresponding hardware accelerator chiplets, and monitor processing status and the status of each hardware accelerator chiplet, dynamically adjusting the number of different types of chiplet accelerators needed.
Yes. Zhongcheng Hualong Computer Technology's patent on a method and chip for implementing self-organizing chiplets describes an architecture where each chiplet has the capability to self-detect and report faults and where upon receiving a fault notification, other chiplets begin competing and negotiating to reallocate resources. This self-organizing resilience model is particularly relevant for aerospace, defense, and automotive applications where a single-point hardware failure cannot be tolerated.
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References
- Architecture of Computing System based on Chiplet — School of Microelectronics, Xidian University, 2022
- Chiplet Heterogeneous Integration Technology — Status and Challenges — National University of Defense Technology, 2020
- Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions — Shanghai Sharetek Technology Co., Ltd., 2022
- Chiplet architecture for a technical system — Robert Bosch GmbH, 2026 (DE, pending)
- Disaggregation of system-on-chip (SOC) architecture — Intel Corporation, 2025 (US, pending)
- Disaggregation of system-on-chip (SOC) architecture — Intel Corporation, 2024 (US, active)
- Disaggregation of system-on-chip (SOC) architecture — Intel Corporation, 2024 (US, active)
- Chiplet architecture for late bind SKU fungibility — Intel Corporation, 2023 (US, active)
- Chiplet architecture for late bind SKU fungibility — Intel Corporation, 2026 (US, active)
- Cache Synchronization for Chiplet Accelerators — Wisconsin Alumni Research Foundation, 2024 (US, active)
- Cache synchronization for chiplet accelerators — Wisconsin Alumni Research Foundation, 2025 (US, active)
- Using chiplet-level performance information for configuring chiplets in a processor — Advanced Micro Devices, Inc., 2023 (WO)
- Packaged device with a chiplet comprising memory resources — Intel Corporation, 2025 (SG, active)
- A quantitative cost model and multi-chiplet architecture exploration — Tsinghua University, 2022
- A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication — Colorado State University, 2022
- SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks — Arizona State University, 2021
- Chiplet-based hardware acceleration method and hardware accelerator — Zhongcheng Hualong Computer Technology Co., Ltd., 2023 (CN, active)
- A method and chip for implementing self-organizing chiplets — Zhongcheng Hualong Computer Technology Co., Ltd., 2023 (CN, active)
- Chiplet-architecture-based chip and control method — Nanjing University of Information Science and Technology, 2024 (CN, active)
- Chiplet arrangement — LTU Licens AB, 2025 (EP, active)
- WIPO — World Intellectual Property Organization: Global Patent Filing Data
- IEEE — Institute of Electrical and Electronics Engineers: Semiconductor and Packaging Standards
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
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