Chiplet Interconnect Patents: Who Leads, Where the Gaps Are 2026
- Filing is still accelerating, not plateauing — the run from 2 families in 2022 to 21 in 2024 says the claim space is being staked out now, not settled.
- One inventor cluster anchors the field: Das Sharma, Choudhary and Onufryk co-file repeatedly, concentrating UCIe-adjacent claims in a small group rather than a single large corporate portfolio.
- The lead has just changed hands — Qualcomm posted the only positive year-on-year momentum in the latest year while the prior filers, including Intel, dropped to zero.
Top-5 share is the combined record count of the five largest assignees divided by all 55 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This dataset tracks patent families describing chiplet interconnect and die-to-die packaging protocols — the physical and link-layer specifications that let separately manufactured dies communicate inside one package. The search combines chiplet architecture and die-to-die interface terminology with protocol-specific language such as UCIe, bump pitch, link efficiency, known-good-die testing and thermal coupling, restricted to the semiconductor-device and digital-processing IPC classes where these claims are actually drafted.
Coverage runs from 2015 through the 2026-07-31 cut-off. Because publication typically lags filing by around 18 months, the most recent one to two years of activity shown here will understate true filing volume once later applications publish.
Filing trend and technology composition
55 published families sit inside the search window, concentrated overwhelmingly in the last three years of the period.
From zero to a 21-family peak
Filings were flat near zero through 2017–2021, reached only 2 families by the 2022 midpoint, then jumped to a peak of 21 in 2024 — a growth curve that is still accelerating rather than levelling off, with 2026 data necessarily partial.
G06F dominates the classification mix
Electric digital data processing (G06F) covers 49 of the records, dwarfing semiconductor-device classification H01L (10) and digital transmission H04L (8). That skew shows the claims here are being drafted primarily as data-processing and interface-control inventions rather than as pure semiconductor-structure patents — a point worth checking before assuming H01L searches alone will surface the relevant prior art.
Shares are the percentage of the 55 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Chiplet Interconnect and Packaging Protocols with Eureka
This page is one run against one query. Ask Eureka your own question about chiplet interconnect and packaging protocols and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this set
Chip-to-chip (D2D) interconnect on package for memory with UCIe PHY
The representative record, filed by Intel and published under EP4684293A1 in early 2026, specifies a die-to-die interconnect on a package built around a UCIe-standard physical layer, applied specifically to memory connectivity between chiplets.Original filing text is in German; the description above reflects the disclosed subject matter.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20220222194A1 | On-package accelerator complex (AC) for integrating accelerator and ios for scalable ran and edge cloud solut… | 14 |
| 2 | US20240311330A1 | On-on-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIE) phy | 9 |
| 3 | US20240095206A1 | Assymmetrical data rates for high speed interconnects | 5 |
| 4 | US20240030172A1 | Three dimensional universal chiplet interconnect as on-package interconnect | 4 |
| 5 | US20250123990A1 | On-package memory with universal chiplet interconnect express | 3 |
| 6 | US20250123989A1 | Optimized transmission and broadcasting of priority packets and critical events via ucie-sideband | 2 |
| 7 | US20240345983A1 | Apparatus, system, and method of communicating management transport packets over a universal chiplet intercon… | 2 |
| 8 | US20250298760A1 | Memory Chiplet Architecture | 1 |
| 9 | US20250094268A1 | Performance And Power Efficient Link Error Recovery In Inter-chiplet Communication | 1 |
| 10 | WO2024196389A1 | On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIE) phy | 1 |
Citation counts inside a searched corpus favour older records; treat them as a signal of influence within this dataset, not as a ranking of current technical importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the numbers mean for a filing decision
Three patterns in this dataset matter more than any single ranking: where volume sits, who is moving, and how tightly the core claims are held.
The claim space opened late and is still moving
A midpoint of just 2 families in 2022 followed by a peak of 21 in 2024 means most of the prior art a new filer will collide with is barely two to three years old. This is not a mature field with settled claim boundaries; it is one where freedom-to-operate searches need refreshing every filing cycle, not once at project start.
Data-processing framing, not just semiconductor structure
Electric digital data processing (G06F) carries the large majority of records, ahead of semiconductor devices (H01L) and digital transmission (H04L). Teams drafting purely from a packaging or physical-layer angle risk missing prior art filed as protocol or interface-control inventions.
The leading filer of the prior period has gone quiet
Intel and the Das Sharma / Choudhary / Onufryk inventor cluster each show a 100% year-on-year drop to zero in the latest year, while Qualcomm is the only tracked assignee still filing and growing. That reversal is worth watching before assuming the historical leader still sets the pace.
A small inventor group, not a broad corporate front
The densest co-filing relationships in this dataset run between three named individuals rather than across a large distributed R&D organisation, meaning a substantial share of the core UCIe-adjacent claim territory traces back to a small group of named inventors.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to chiplet interconnect and packaging protocols, with the prior art for and against each one.
Who is filing, and where the field is open
Assignee activity is split between a large corporate filer group and a tight inventor cluster; recent momentum favours neither of the historical leaders.
Qualcomm is the only assignee still accelerating
Where every other tracked assignee — including Intel and the core inventor cluster — dropped to zero filings in the latest year, Qualcomm posted 3 families and positive growth, making it the one name in this dataset currently expanding its position rather than defending one.
Intel's filing pace has stalled inside this window
Intel's representative record (EP4684293A1) dates to early 2026, but the assignee-level trend shows zero new families in the latest tracked year, a sharp reversal from earlier activity and a signal that its UCIe-related claim strategy may be shifting to prosecution of existing applications rather than new filing.
Core UCIe claims trace to a named inventor group
Das Sharma, Choudhary and Onufryk co-appear across the strongest co-assignee pairs in the dataset, all now at zero latest-year filings — a cluster whose historical output anchors much of the die-to-die interface claim language other filers will need to design around.
| Assignee | Recent year | YoY |
|---|---|---|
| Qualcomm Incorporated | 3 | +50% |
| Intel Corporation | 0 | -100% |
| DAS SHARMA DEBENDRA | 0 | -100% |
| CHOUDHARY SWADESH | 0 | -100% |
| ONUFRYK PETER | 0 | -100% |
| MediaTek Inc. | 0 | -100% |
| Shanghai Biren Technology Co., Ltd. | 0 | -100% |
| Samsung Electronics Co., Ltd. (Korea) | 0 | -100% |
Where to take this analysis
The dataset points to open branches and a fast-moving leader board rather than a settled field — both are reasons to model specific claim scenarios rather than rely on the summary view.
Stress-test a claim against the inventor cluster
Run a candidate die-to-die interface claim against the Das Sharma / Choudhary / Onufryk family set specifically, since that cluster holds the densest concentration of related claim language in this dataset.
Explore in EurekaTrack Qualcomm's filing direction
With Qualcomm the only assignee showing positive year-on-year momentum, monitoring its newest filings is a more current signal than the historical citation leaders.
Explore in EurekaMap the under-claimed branches
Known-good-die testing and thermal coupling show thin coverage relative to core UCIe claims — worth a focused search before committing R&D there.
Explore in EurekaCommon questions on chiplet interconnect patents
UCIe (Universal Chiplet Interconnect Express) is an industry-standard physical-layer and protocol specification for connecting chiplets within a single package. It shows up repeatedly in this dataset because it gives filers a shared vocabulary — bump pitch, link efficiency, PHY architecture — that patent drafters reuse across many related claims. Its prominence in the most-cited records here reflects how central the standard has become to how die-to-die connectivity claims are written, not that the standard itself is patented.
Filing activity in this dataset splits between corporate assignees such as Intel and Qualcomm and a named inventor cluster (Das Sharma, Choudhary, Onufryk) whose co-filed families concentrate a large share of the core die-to-die interface claims. Recent-year momentum has shifted: Qualcomm is the only tracked assignee still filing and growing, while the historical leaders show zero filings in the latest year. Any competitive read should weight recency, not just cumulative family counts.
Filing accelerated sharply between 2022 and 2024, moving from 2 families to a peak of 21, and shows no sign of plateauing within the tracked window. The 2025 and 2026 figures will read lower simply because publication lags filing by roughly 18 months, so recent-year totals are undercounts rather than a genuine slowdown. Treat the 2024 peak as the clearest completed signal available and expect upward revision to the years after it.
Relative to the dense core claim territory around UCIe PHY and die-to-die interface protocols, sub-areas such as known-good-die test protocols, thermal coupling across stacked chiplets, and bump-pitch scaling below current nodes carry comparatively thin coverage in this dataset. That does not mean these areas are unpatented elsewhere, but within this search scope they represent claim territory that has not been heavily staked out yet, making them worth a dedicated freedom-to-operate check before committing to a specific implementation.
Patent families are the fairer unit here than raw publication counts, since families neutralise the effect of aggressive continuation filing and multi-jurisdiction duplicates — this dataset already reports family-level counts. High filing density in a sub-area, such as the G06F-classified data-processing claims, indicates that claim space is occupied rather than that the underlying technology is mature or proven, so density alone should not be read as a quality signal.
Research Chiplet Interconnect and Packaging Protocols in depth with Eureka
Go past this page: query the whole chiplet interconnect and packaging protocols corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.