This landscape covers mechanisms that let a die-to-die or chiplet interconnect link continue operating despite a defective or degraded lane, rather than requiring the package to be discarded. That includes spare lane remapping, runtime lane degradation detection and handling, spare bump allocation under tight bump-pitch constraints, and the yield relationship between repairable interconnect design and packaging economics. It spans 6,841 published records filed between 2015 and mid-2026, drawn from IPC classes centred on memory (G11C), digital processing (G06F) and digital transmission (H04L).

Filing is concentrated at the top of the ranking but not dominated by a single company: the leading assignee holds 718 records, and the top five combined account for 30.1% of all 6,841 records in scope. That still leaves roughly seven in ten records spread across a long tail of the remaining ranked companies, which include major memory, foundry and systems firms active in this space. The ranking covers 100 companies total and should not be read as a top-50 or top-100 exclusivity list.

No — filing peaked in 2019 at 205 records and has generally trended down since, with the 2022 midpoint at 183 and a much lower count in the most recent, still-partial year. This pattern suggests the foundational repair and redundancy architectures were claimed relatively early in the field's history. Because publication lags filing by around 18 months, the final year or two of any trend chart will always look lower than it will eventually turn out to be, so the true recent-year picture is likely somewhat higher than shown.

US20260003749A1, filed by Microsoft Technology Licensing, describes a multi-die system where each die's modular die-to-die link macro exposes a fixed number of data lanes, and where repair groups spanning some or all of those lanes each independently designate a configurable number of redundant lanes. The key technical feature is that the group size and redundancy count are independently configurable per repair group rather than fixed system-wide. Anyone designing a lane-repair scheme with per-group configurable redundancy ratios should review this filing's specific claim boundaries before assuming a clear path.

Relative to the dense core of memory-adjacent repair claims under G11C and G06F, filing density thins out in areas like runtime lane degradation telemetry, bump-pitch-constrained spare allocation schemes, and package-level cross-die spare lane remapping. These are not unclaimed, but they carry noticeably fewer records than the core repair-group and redundancy-ratio claims. A first claim in these areas would likely need to combine a specific detection or telemetry mechanism with a concrete packaging constraint, rather than claim redundancy switching in the abstract.