Filing in this space is concentrated at the top: the leading assignee holds 49 of the 515 records in scope, with the next four ranked assignees combining for a total top-5 share of 143 records, or 27.8% of the field. The ranked list runs across 100 assignees, so beyond the top 10 (44.1% combined) the picture is a long tail of companies with only a handful of filings each. Large semiconductor and interface-IP firms make up most of the concentrated top tier, reflecting that CDR circuits are usually filed as part of larger SerDes or transceiver product portfolios rather than standalone patent programs.

Filing volume has effectively plateaued rather than grown or declined: 2021 and 2024 both recorded 10 filings each, a 0% change across that three-year span, after an earlier peak of 24 filings in 2018. The years after 2024 look lower in the raw trend line, but that is expected — publication typically lags actual filing by around 18 months, so 2025 and 2026 figures are still filling in and should not be read as a real drop. The honest read is a mature, steady filing rate rather than either momentum or decline.

The two dominant IPC subclasses are H04L (digital information transmission), touching 69.5% of the 515 records, and H03L (automatic frequency/phase control), touching 47.6%. These overlap heavily because CDR circuits are usually claimed as part of a transmission link or receiver, with the loop and PLL mechanics classified under H03L. Secondary classes include H04B general transmission (15.7%), H03D demodulation (9.7%), H04J multiplexing (7.4%), H03K pulse and logic technique (6.0%), and G01R measurement and G11B storage at 4.9% each — since records often carry multiple classes, these shares add up to well over 100%.

US11128304B1, assigned to Novatek Microelectronics and granted in 2021, claims a jitter tolerance enhancement circuit layered onto a conventional CDR loop: it sits on the data input path, detects a correlation between the incoming data signal and the recovered clock, and adjusts the loop gain of the CDR circuit in response. It does not claim a new clock recovery topology outright — it claims the specific mechanism of correlation-based loop-gain adjustment for jitter tolerance improvement. A design that achieves jitter tolerance through a different mechanism, such as fixed multi-stage filtering or a different bandwidth-adaptation scheme, would sit outside this specific claim scope, but any implementation using correlation-driven gain adjustment on the data-to-clock path should be checked against it directly.

Relative to the dense core of loop-bandwidth and phase/frequency-control claims (H03L at 47.6% of records), several adjacent mechanisms show thinner coverage in this dataset: phase interpolator resolution scaling, spread-spectrum clock tracking loops, sub-rate lock-time acceleration, reference-clock jitter injection compensation, and multi-lane CDR skew calibration. These are not unclaimed territory outright, but they carry less filing density than the core loop-control claim space, making them worth a closer freedom-to-operate check before assuming they are blocked.