Clock Generation & PLL Patents: Who Leads, Filing Trends 2026
- Filing has cooled since 2017. the peak year logged 149 families and the midpoint year (2022) sits at 111 — the trend line points down, not up, through the most recent full years of data.
- Six IPC subclasses beyond H03L carry meaningful volume. H04L, H03K, H04B, G06F, H03B, H03C together account for thousands of records, showing PLL claims are increasingly bundled with digital and RF system claims rather than filed as standalone oscillator art.
- The largest named assignees show zero filings in the latest year. every incumbent tracked in recent-year momentum reports 0 filings in the most recent year, which reads more as a publication-lag artefact than a real exit — but it changes how you read 'who is active now'.
Filing growth compares 2021 (111 records) with 2024 (100) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 6,745 records in scope (CR5), not by the ranked leaders only.
What the clock generation and PLL patent record shows
Clock generation and phase-locked loop (PLL) design sits at the intersection of analog circuit engineering and digital system timing. The claim space covers fractional-N synthesizers, jitter and spur suppression, lock-time reduction, and supply-noise rejection techniques that keep a synthesized clock stable enough for RF, data-converter and digital-logic applications. Because a PLL block is embedded inside almost every mixed-signal chip, filings in this space cross into digital transmission (H04L), pulse and logic circuits (H03K), and general RF transmission (H04B) as often as they sit purely in the core oscillator subclass H03L.
The dataset spans 2015 through the 2026 cut-off, with 6,745 published families indexed against IPC classes H03L7, H03B21 and H03K3 and filtered to abstracts or claims mentioning jitter, lock time, spur, fractional-N or supply noise rejection. Publication lags filing by roughly eighteen months, so the last one to two years in any trend understate real filing activity.
Filing trend and technology composition
The two views below separate when filings happened from where they were classified, which together explain both the slowdown and the spread of the art into adjacent domains.
A declining trend from a 2017 peak
Filings peaked at 149 in 2017, held at 111 by the 2022 midpoint, and continued declining toward the 2026 cut-off (5, a partial year). Read the last one to two years as undercounted rather than as a genuine collapse in activity, since publication lag pushes recently filed applications out of the visible record.
H03L dominates, but seven other subclasses carry real volume
H03L accounts for 6,523 of the 6,745 records, confirming this is the core classification for the search. H04L (1,005), H03K (808), H04B (570), G06F (445), H03B (437), H03D (348) and H03C (290) show that PLL and clock-generation claims are routinely filed alongside digital transmission, logic-circuit and RF modulation claims rather than in isolation — a sign that timing IP increasingly rides inside larger system-level filings.
Shares are the percentage of the 6,745 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Clock Generation and PLL Design with Eureka
This page is one run against one query. Ask Eureka your own question about clock generation and pll design and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records anchor the prior art baseline
US7274231B1 — Low jitter frequency synthesizer
A frequency synthesizer IC that pairs a variable delay circuit with a fractional-N phase locked loop and a feedback loop: the variable delay circuit sits at the PLL input, the feedback loop routes a first control signal from the PLL back to the delay circuit, and the delay circuit produces a reference signal whose phase delay tracks both control signals. The fractional-N PLL then uses that reference to generate its own control and output signals.Filed by Integrated Device Technology, Inc.; granted 2007-09-25.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6008703A | Digital compensation for wideband modulation of a phase locked loop frequency synthesizer | 472 |
| 2 | US5485490A | Method and circuitry for clock synchronization | 451 |
| 3 | US20060029177A1 | Unified digital architecture | 438 |
| 4 | US5535432A | Dual-mode satellite/cellular phone with a frequency synthesizer | 385 |
| 5 | US6384690B1 | Phase locked loop control via inner and outer feedback control circuits | 289 |
| 6 | US5544203A | Fine resolution digital delay line with coarse and fine adjustment stages | 252 |
| 7 | US5834987A | Frequency synthesizer systems and methods for three-point modulation with a DC response | 247 |
| 8 | US5604468A | Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the … | 245 |
| 9 | US4893271A | Synthesized clock microcomputer with power saving | 240 |
| 10 | US6429693B1 | Digital fractional phase detector | 221 |
Citation counts inside a searched corpus favour older records that have had more years to accumulate citations; treat this list as a signal of foundational influence, not of what matters most today.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing or freedom-to-operate decision
Three patterns stand out once volume, classification and citation data are read together: where the claim density sits, what shape the filer base takes, and how much weight to give older influential patents.
The core art is contracting, not expanding
From a 2017 peak of 149 filings to a midpoint of 111 in 2022 and a sharply lower 2026 partial count, the trend line is flat-to-declining rather than growing. New entrants should expect a mature, well-mapped claim landscape rather than fresh open ground in core PLL architecture.
PLL claims increasingly ride inside system filings
H04L, H03K, H04B and G06F volumes indicate that jitter and lock-time innovations are as often claimed as part of a digital transmission or data-processing system as they are filed as standalone oscillator patents. Searches limited to H03L7 alone will miss a meaningful share of relevant claims.
Recent-year momentum is muted across the board, not just at one firm
Every large assignee tracked for recent-year momentum shows zero filings in the latest year. Given the eighteen-month publication lag, this is best read as a visibility gap rather than a genuine industry-wide halt, but it means recent competitive activity cannot yet be confirmed from published records alone.
Foundational patents still anchor prior-art searches
The most-cited records date from the 1990s and 2000s and cover wideband modulation compensation, clock synchronization and unified digital architectures. Their citation counts reflect decades of accumulation, not current relevance — any freedom-to-operate review still needs to check them, but recent filings won't show comparable citation depth yet.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to clock generation and pll design, with the prior art for and against each one.
Who holds the claim space, and where the gate sits for new entrants
Co-assignee pairings show that this space is largely built on corporate-family filing (parent and regional subsidiary pairs) rather than cross-company joint development, and the largest filers span the full range from IDM chipmakers to systems and telecom incumbents.
A broad, distributed filer base
The ranking spans semiconductor IDMs, telecom equipment makers, and systems companies, with corporate-family pairs (parent plus national subsidiary) among the strongest co-assignee links rather than external collaborations.
Co-filing reflects corporate structure, not partnership
The strongest pairs link a parent company to its own regional subsidiary or IP department rather than two independent firms, indicating most co-assignment here is an artefact of how multinational filers structure their patent holding entities.
Filing is US-centred with strong EPO, Japan and PCT routes
United States filings lead by a wide margin, followed by Europe, Japan, WIPO/PCT, China and South Korea. A freedom-to-operate check limited to one jurisdiction will miss substantial parallel filings, particularly at the EPO and via PCT.
| Assignee | Recent year | YoY |
|---|---|---|
| Motorola, Inc. | 0 | — |
| Telefonaktiebolaget LM Ericsson | 0 | — |
| Samsung Electronics Co., Ltd. | 0 | — |
| Qualcomm Incorporated | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Texas Instruments Incorporated | 0 | — |
| Intel Corporation | 0 | — |
| NEC Corporation | 0 | — |
Where to take this analysis
The dataset points to specific follow-up work depending on whether the goal is freedom-to-operate, competitive tracking, or identifying open claim space.
Run a claims-level check against the most-cited records
Citation depth on records like US6008703A and US5485490A signals foundational coverage of modulation compensation and clock synchronization; a claims chart against current designs is the fastest way to confirm exposure.
Explore prior art in EurekaTrack the under-claimed sub-areas before they fill in
Supply-noise rejection and digital-to-time converter calibration show thinner claim density than the core PLL art; monitoring new filings in these branches now costs less than reacting after a competitor stakes the ground.
Set up monitoring in EurekaVerify recent assignee activity beyond the published record
Zero latest-year filings across every tracked incumbent likely reflects publication lag rather than a real slowdown; cross-check against pending applications and non-patent literature before drawing competitive conclusions.
Search live filings in EurekaCommon questions about clock generation and PLL patents
The tracked filing trend peaked at 149 families in 2017, held near 111 by 2022, and drops further toward the 2026 cut-off. Part of that recent drop is a publication-lag artefact, since patent applications typically take about eighteen months to publish, so 2025 and 2026 figures are undercounted rather than final. Even accounting for lag, the mid-decade trend shows flat-to-declining activity rather than growth, consistent with a mature core PLL architecture where the basic building blocks are well established and most new value comes from system integration rather than the core oscillator circuit.
H03L (automatic frequency and phase control) is the anchor class with 6,523 of 6,745 records, but limiting a search to H03L alone misses real volume. H04L (digital information transmission), H03K (pulse technique and logic circuits), H04B (transmission generally) and G06F (digital data processing) each carry hundreds of relevant records, reflecting how jitter, lock-time and fractional-N claims are frequently bundled into system-level filings rather than filed as pure oscillator patents. A thorough search should span at least these classes alongside H03L7, H03B21 and H03K3.
Not necessarily. Every large assignee tracked for recent-year momentum in this dataset shows zero filings in the latest year, but that pattern appears across the board, not at a single company, which points to a data visibility issue rather than a genuine industry-wide stop. Published patent records lag actual filing dates by roughly eighteen months, so the most recent one to two years will always understate real activity for every filer. Confirming current competitive activity requires checking pending applications, product launches and non-patent literature alongside the published patent record.
US7274231B1 claims a specific architecture: a variable delay circuit at the PLL input, a fractional-N phase-locked loop, and a feedback loop that routes a control signal from the PLL back to the delay circuit so the delay circuit's output phase tracks that feedback. Anyone designing a low-jitter fractional-N synthesizer with a comparable delay-feedback arrangement should map their circuit topology against this claim structure specifically, rather than assuming general fractional-N art clears it. It sits among the representative filings from Integrated Device Technology and is a useful anchor point for a claims-chart exercise, though it should be checked against the full most-cited list and current claim scope, not read in isolation.
The clearest openings sit in branches with thinner claim density relative to the dominant H03L core: supply-noise rejection specifically for fractional-N loops, sub-nanosecond lock-time control schemes, spur suppression tuned for multi-GHz synthesizer outputs, digital-to-time converter calibration, and cross-domain jitter cancellation for mixed-signal SoCs. These are narrower than the core PLL art but still active enough to matter, since PLL blocks are embedded across RF and digital-logic products. A first claim in these areas should specify the calibration or feedback mechanism precisely, since generic fractional-N or jitter-suppression language is likely to run into the dense prior art already covered by the top-cited records.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.