CMOS Image Sensor Patents: Who Leads, Where Filings Stall 2026
- Filing has cooled sharply since its 2017 peak. Annual filings ran at 209 in 2017 and had fallen to single digits by the most recent full year, with the 2022 midpoint at 98 — the claim space built up fast and then growth flattened.
- H01L dominates the IPC mix, H04N is a strong second. 2,776 of 3,418 records sit under H01L (semiconductor devices) versus 1,922 under H04N (pictorial communication), showing the field is claimed primarily as device structure, not downstream image processing.
- The United States receives more than twice China's filings. 1,837 records route through the USPTO against 384 in China, 318 at the EPO, 283 in South Korea, 166 in Japan and 162 in Taiwan — filing strategy still centres on the US docket.
What this landscape covers
This landscape tracks 3,418 patent families published between 2015 and mid-2026 that combine CMOS image sensor architecture claims with pixel-level performance language — quantum efficiency, dark current, global shutter, stacked sensor and dynamic range — under the semiconductor device and image-communication IPC classes. The scope deliberately excludes general camera-module and downstream software patents to keep the focus on sensor-die architecture and pixel physics.
Because publication typically lags filing by around eighteen months, the last one to two years in any trend chart will look thinner than they eventually turn out to be. That lag does not explain the decline visible from the 2017 peak onward, which spans multiple full reporting years.
Filing trend and technology composition
Two views of the same corpus: how filing volume has moved over time, and how the claims are distributed across IPC subclasses.
A 2017 peak followed by a steady decline
Filings peaked at 209 in 2017, held near the 98 mark by 2022, and have since tapered to single digits in the most recent (partial) year. Read the decline as a maturing claim space rather than a shrinking market: sensor shipments have kept growing even as the rate of new architecture claims has slowed.
Device structure claims outweigh image-processing claims
H01L (semiconductor devices) covers 2,776 of the 3,418 records and H04N (pictorial communication) covers 1,922, with H10D, H10P and H10W adding smaller general-semiconductor buckets. Optical elements (G02B) and image data processing (G06K, G06T) together account for under 200 records, confirming this corpus is a die-and-pixel landscape rather than an optics or software one.
Shares are the percentage of the 3,418 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on CMOS Image Sensor Technology with Eureka
This page is one run against one query. Ask Eureka your own question about cmos image sensor technology and every answer comes back with the patent numbers behind it.
Try EurekaThe patents everyone in this space cites
US8471315B1 — CMOS image sensor with dual-channel dark-current drain
The invention describes a solid-state CMOS image sensor array with pixels supporting both global and rolling shutter modes, using a dual-channel transfer-storage gate for charge transfer from photodiode to floating diffusion. A shallow surface channel drains dark current away from the pixel while a buried bulk channel handles standard charge transfer and storage, improving noise performance and reducing shading artifacts.Filed by Aptina Imaging Corporation, granted 2013-06-25.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US5461425A | CMOS image sensor with pixel level A/D conversion | 615 |
| 2 | US6168965B1 | Method for making backside illuminated image sensor | 379 |
| 3 | US6169319B1 | Backside illuminated image sensor | 329 |
| 4 | US6137100A | CMOS image sensor with different pixel sizes for different colors | 315 |
| 5 | US20060274171A1 | Digital picture taking optical reader having hybrid monochrome and color image sensor array | 311 |
| 6 | US20140160259A1 | Camera system with minimal area monolithic CMOS image sensor | 205 |
| 7 | US20150350583A1 | Imaging systems having image sensor pixel arrays with sub-pixel resolution capabilities | 196 |
| 8 | EP1670062A1 | Local interconnect structure for a CMOS image sensor and its manufacturing method | 195 |
| 9 | US20060108613A1 | CMOS image sensor | 195 |
| 10 | US6184055B1 | CMOS image sensor with equivalent potential diode and method for fabricating the same | 172 |
Citation counts accumulate over time inside a searched corpus, so older foundational filings will always show higher counts than recent ones — treat this as a map of influence, not of current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three patterns stand out once the raw counts are set against the timeline and the assignee momentum figures.
The architecture land-grab is largely over
Most of the structural claim space around backside illumination, pixel-level A/D conversion and stacked die architecture was staked out between roughly 2015 and 2020. Recent-year filings from the largest historical assignees have fallen to zero or near-zero, which reads as consolidation of an established claim map rather than retreat from the market.
US docket still anchors global strategy
The USPTO receives more than double the filings of the next largest office (China), with the EPO, South Korea, Japan and Taiwan trailing further behind. For a company entering this space, a freedom-to-operate check that skips the US filing is checking the smaller half of the picture.
Device physics, not image pipelines, carries the claim density
Nearly all activity sits in semiconductor-device classes rather than image-processing classes. Companies differentiating on downstream algorithms rather than pixel architecture are filing into comparatively open ground.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to cmos image sensor technology, with the prior art for and against each one.
Who holds the claim space
Filing counts concentrate among a small set of sensor manufacturers and semiconductor foundries, with momentum now flat or negative even for the largest historical filers.
Sony's filing pace has flattened
Sony Group shows zero filings in the latest tracked year, and its Sony Semiconductor Solutions unit shows a 100% year-on-year drop. That is consistent with a portfolio that has already secured its core stacked-sensor and global-shutter claims rather than one losing ground.
Foundry-side filing is thinning too
TSMC recorded a single filing in the latest year, down 50% year-on-year, and OmniVision recorded zero, down 100%. Foundry and fabless sensor filers appear to be following the same late-cycle pattern as the integrated device manufacturers.
Co-filing is rare and academically anchored
Only ten co-assignee pairs appear across the corpus. The strongest links pair Samsung Electronics with Yonsei University's technology transfer arm and Samsung Electro-Mechanics, and pair Sony with Parkes Inc., suggesting sensor makers lean on university labs for specific pixel-physics problems rather than broad joint filing programmes.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Company (TSMC) | 1 | -50% |
| OmniVision Technologies, Inc. | 0 | -100% |
| Sony Group Corporation | 0 | — |
| Sony Semiconductor Solutions Corporation | 0 | -100% |
| Samsung Electronics Co., Ltd. | 0 | — |
| Dongbu Electronics Co., Ltd. | 0 | — |
| Magnachip Semiconductor Ltd. | 0 | — |
| Semiconductor Components Industries, LLC (ON Semiconductor) | 0 | — |
Turning this landscape into a filing decision
The counts above describe where claim density already sits. Deciding where to file next means testing a specific claim draft against that density, not just reading the chart.
Check freedom-to-operate on a specific pixel structure
Run the exact transfer-gate or dark-current-drain language you plan to claim against the dense H01L cluster before drafting, rather than after.
Run a freedom-to-operate checkTrack the under-claimed branches as they fill in
Event-driven readout and on-chip HDR circuits show lighter density now; set an alert so a competitor filing there does not surprise you later.
Set up monitoringMap the co-filing network before approaching a university lab
The strongest co-assignee pairs are university tech-transfer offices; knowing who already partners with whom shapes who will take a licensing call.
Explore assignee networksCommon questions about CMOS image sensor patents
Filing is concentrated among a small group of integrated sensor manufacturers and semiconductor foundries, including Sony, Samsung Electronics, TSMC and OmniVision, based on family counts in this dataset. Sony's holdings span both its parent Sony Group and its dedicated Sony Semiconductor Solutions unit, which file separately but cover overlapping pixel-architecture ground. None of these assignees show strong filing growth in the most recent tracked year, which points to a portfolio-defence phase rather than an active land-grab.
Filings peaked at 209 in 2017 and have fallen every year since, reaching single digits by the latest tracked year. This pattern is typical of a technology that went through a rapid structural land-grab — backside illumination, stacked die, global shutter pixel design — and then consolidated once the core architectures were claimed. It does not mean the underlying market has shrunk; sensor shipment volumes and IPC-classified filing counts are not the same measure, and publication lag means the very last year or two is always undercounted.
H01L covers semiconductor device structure — the physical pixel, transistor and stacking architecture of the sensor die — and accounts for 2,776 of the 3,418 records in this corpus. H04N covers pictorial communication, meaning image and video signal processing built around the sensor output, and accounts for 1,922 records. A filer building a novel pixel transfer-gate structure should search H01L most closely; a filer building novel HDR or color-processing logic on top of a standard sensor should weight H04N and the smaller G06T bucket instead.
US8471315B1, assigned to Aptina Imaging Corporation and granted in 2013, claims a CMOS pixel design using a dual-channel transfer-storage gate: a shallow surface channel that drains dark current away from the pixel and a separate buried bulk channel that carries the normal charge-transfer and storage function. It supports both global and rolling shutter operation in the same pixel. Anyone designing a global-shutter pixel with a dedicated dark-current drain path needs to check this claim scope specifically, since the dual-channel structure is the novel element rather than global shutter operation on its own.
The clearest gaps sit outside the dense H01L pixel-architecture cluster: event-driven pixel readout, on-chip HDR tone-mapping circuits, hybrid monochrome-color pixel arrays, sub-pixel dark-current calibration methods and wafer-stacked ADC partitioning all show comparatively light claim density in this corpus's IPC and citation pattern. These are adjacent to, rather than inside, the most heavily cited prior art, which makes them a more realistic place to build a defensible new claim than the core dark-current or global-shutter pixel structures.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.