CMOS under array builds the peripheral logic directly beneath the memory or sensor array on a single substrate, sharing one process flow and thermal budget. Bonded array architecture fabricates the array and the logic on separate wafers or dies, each optimised for its own process, and then joins them, typically through wafer-to-wafer or die-to-wafer bonding. The bonded approach lets a manufacturer use a more advanced logic node without forcing the array to tolerate that node's thermal or process constraints, which is why bonding-specific claims around pad pitch and alignment have become a distinct filing area.

The leading assignee in this dataset holds 5,558 records, well ahead of the fifth-ranked filer at 2,242 and the tenth-ranked filer at 1,910. The five leading assignees together account for 15,565 records, 9.5% of the 164,392 records in scope, and the top ten reach 15.7%. That leaves the large majority of filings spread across a long tail of other companies, so leadership at the top does not mean the field is closed to new entrants.

No, filing volume has already passed its peak. Records rose from 834 in 2017 to a peak of 972 in 2021, then eased back toward 764 at the 2022 midpoint, and recent-year momentum figures show steep year-over-year declines across the leading assignees. The most recent year's count will understate true activity because publication typically lags filing by around 18 months, but the broader trend across the period is flat to declining rather than accelerating.

Foundational claims tied to separating array and peripheral fabrication steps, such as those in US5292681A, describe the basic pattern of building a memory array with one process sequence and CMOS peripheral transistors with another on the same wafer. Because this pattern underlies most later under-array and bonded-array implementations, later filers generally design around it through the specific bonding, alignment or test-access mechanics rather than the core separation concept itself, since that concept sits in older, broadly cited prior art rather than in a single currently enforceable position for most jurisdictions.

Narrower IPC subclasses such as H10P, H10D and H10W each account for under 1.5% of the 164,392 records in scope, well below the 6.7% held by the general H01L semiconductor device class. That gap suggests claim space specific to bonding pad pitch scaling, post-bond test access and thermal budget separation between tiers is comparatively lightly claimed relative to broad device-level integration claims, making these narrower mechanics a more promising area for a first-mover filing strategy than the crowded general device classes.