CFET Advanced Materials Patents: Who Leads, Where Gaps Are 2026
- Filing has already peaked. 2022 was the high point at 5 families in a year, and the count has not grown since — this is a narrow, still-forming niche, not an expanding one.
- One record dominates citations. US20190172755A1 carries 91 citations, more than three times the next most-cited record, marking it as the reference point everyone in multi-channel-material CFET design works around.
- Filing is US-centric. Nine of the tracked records went through the USPTO versus three PCT filings and one at the EPO, so design-around strategy should start with US claim scope.
Filing growth compares 2021 (2 records) with 2024 (0) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this landscape covers
Complementary FET (CFET) stacks two transistor channels vertically to keep scaling density up as planar and even lateral gate-all-around designs run out of room. The advanced-materials slice of that field — the choice and integration of high-mobility, 2D, or SiGe channel material inside a stacked CFET — is a small, technically dense pocket of the broader CFET patent set, not a mass-filed category. Thirteen patent families meet the search criteria across the tracked window, which is a signal of how early and how narrow this specific integration problem still is.
Because publication typically lags filing by around 18 months, the most recent one or two years in any trend chart will look thinner than they will eventually turn out to be. Treat the tail of the trend line as provisional, not as a signal of retreat.
Filing trend and technology composition
Two views of the same 13-family set: how filing has moved year over year, and which classification codes the records sit under.
A flat curve, not a rising one
Filing starts at zero in 2017, climbs to a peak of 5 families in 2022, and has not exceeded that midpoint since — read together with the publication lag, this points to a technology that found a small group of committed filers early and has not attracted a wider wave behind them.
Concentrated in core semiconductor-device classes
All 13 records sit under H01L (semiconductor devices), with 6 also tagged under the newer H10D general semiconductor-device class and a single record under H10P — consistent with a field still being classified under legacy codes as reclassification catches up with CFET-specific subject matter.
Shares are the percentage of the 13 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Complementary FET Advanced Materials with Eureka
This page is one run against one query. Ask Eureka your own question about complementary fet advanced materials and every answer comes back with the patent numbers behind it.
Try EurekaThe records other filers build around
Method for incorporating multiple channel materials in a CFET device
A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of…Abstract trimmed to its operative claim language; full text and file history are available in Eureka.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20190172755A1 | Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) devi… | 91 |
| 2 | US10685887B2 | Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) devi… | 27 |
| 3 | US20230178435A1 | Complementary FET (CFET) devices and methods | 21 |
| 4 | US20230377998A1 | Method of forming confined growth s/d contact with selective deposition of inner spacer for cfet | 19 |
| 5 | US20240203990A1 | Stacked CMOS devices with two dielectric materials in a gate cut | 12 |
| 6 | WO2021066951A1 | Method of making multiple NANO layer transistors to enhance a multiple stack CFET performance | 5 |
| 7 | US20250120143A1 | Extended drain transistor for high voltage applications | 2 |
Citation counts inside any searched corpus skew toward older filings simply because they have had longer to accumulate references — read this table as a map of influence, not of current filing activity.
Publication numbers are shown where the record carries one (7 of 7 rows); clicking a row searches Eureka by that number.
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Three signals stand out once the family-level data is put together: a plateaued filing curve, a heavily-cited anchor patent, and a jurisdictional skew toward the US.
Growth already flattened
The filing curve peaks at 5 families in 2022 and has not been matched since. Combined with the 18-month publication lag, the honest reading is 'plateaued and unclear whether it resumes' rather than 'declining' — but it is not the accelerating curve you'd expect from a technology entering a scale-up phase.
One filing anchors the field
US20190172755A1 has more than three times the citations of the next-ranked record. New filers in multi-channel-material CFET integration are almost certainly citing it or designing explicitly around its claim scope.
US-first filing behaviour
Nine records were filed through the USPTO, three via PCT, and one at the EPO. Freedom-to-operate work outside the US has comparatively little dedicated coverage in this specific dataset, which is worth confirming before assuming clearance abroad.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to complementary fet advanced materials, with the prior art for and against each one.
A small group of foundries, IDMs and equipment makers
With only 13 families in the set, the assignee list is short and the co-filing pattern is limited to a handful of pairs — mostly parent-subsidiary relationships inside the same corporate group.
International Business Machines Corporation (IBM) (IBM)
IBM's filings, together with its China and UK IP-department co-assignee pairings, point to a centrally coordinated global filing strategy rather than independent regional efforts.
Tokyo Electron Limited (Tokyo Electron)
Tokyo Electron's co-filing with its US holding entity, and its authorship of the representative record in this set, mark it as a process-integration specialist working the multi-channel-material problem from the equipment side rather than the device-architecture side.
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) (TSMC)
TSMC's presence in the assignee list without a matching uptick in the most recent year is consistent with the plateaued trend — a foundry with existing coverage in this narrow niche, not one still expanding its claim footprint here.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | — |
| Tokyo Electron Limited | 0 | — |
| Intel Corporation | 0 | — |
| IBM (China) Co., Ltd. | 0 | — |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | — |
| Tokyo Electron U.S. Holdings, Inc. | 0 | — |
| IBM UNITED KINGDOM LTD INTELLECTUAL PROPERTY DEPARTMENT | 0 | — |
Where to take this next
The family-level dataset behind this page supports closer, claim-by-claim work than the summary view above.
Check freedom-to-operate against the anchor patent
US20190172755A1's 91 citations make it the record most likely to be asserted or cited against a new multi-channel-material CFET filing. A claim chart against it is the first step before committing engineering resources.
Run a claim comparison in EurekaMap the under-claimed branches
2D-channel integration and gate-cut dielectric pairing show thin coverage in this set. Confirming that thinness holds across the full unfiltered corpus, not just this search string, is worth doing before relying on it.
Explore white space in EurekaCommon questions about CFET advanced-materials patents
A CFET stacks an n-type and a p-type transistor vertically in the same footprint, rather than placing them side by side, to keep transistor density scaling as planar area runs out. Because the two channels are built at different heights in the same stack, they often need different channel materials — for example a SiGe channel for one polarity and a silicon or 2D-material channel for the other — to get comparable mobility for both electrons and holes. Patent filings in this niche focus specifically on how to integrate those different materials into one stacked structure without damaging either channel during processing.
The most-cited record in this dataset, US20190172755A1, has 91 citations, well ahead of any other filing in the set, and its related grant US10685887B2 is separately cited 27 times. Both describe methods for incorporating multiple channel materials into a CFET device, which makes them a natural reference point for later filers. Beyond that anchor, filing is spread thinly across a small group of IDMs, foundries and semiconductor-equipment makers rather than concentrated behind one dominant portfolio holder.
Based on the tracked filings, no — the yearly count peaked at 5 families in 2022 and has not exceeded that since, giving a flat rather than rising curve. That said, patent publication typically lags actual filing by around 18 months, so the last one or two years in any such dataset will always look artificially quiet. The fair reading is that this is a small, plateaued niche whose near-term trajectory is not yet confirmed either way, rather than one in clear decline.
In this dataset, sub-areas like 2D semiconductor channel integration into stacked CFET structures, SiGe-to-III-V transition schemes, and gate-cut dielectric pairing for stacked CMOS show noticeably thinner dedicated claim coverage than the core multi-channel-material integration methods. A new filer targeting one of these branches would likely face less directly-blocking prior art than one filing squarely on the anchor patent's territory. Confirming that gap against the full unfiltered patent corpus, not just this search string, is a sensible next step before committing to a claim strategy.
Nine of the 13 tracked records were filed through the USPTO, three as PCT applications, and one at the EPO, so the US is clearly the primary filing venue in this niche. That skew means freedom-to-operate analysis should start with US claim scope, but it also means coverage outside the US — particularly in East Asian markets where much of the fabrication actually happens — may be comparatively thin in this specific dataset. Anyone relying on that apparent gap should verify it against broader search terms, since a narrow search string like this one can understate filings that use different terminology in non-US jurisdictions.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.