A complementary FET stacks an n-type and a p-type transistor vertically on top of each other rather than placing them side by side, which shrinks the footprint of a logic cell. In advanced packaging contexts, CFET claims often intersect with backside power delivery, 3D integration and hybrid bonding because the stacked devices need vertical interconnects and power rails routed from the back of the wafer. This corpus shows CFET claims classified overwhelmingly under core semiconductor-device codes (H01L, H10D), meaning most filings so far address the device and contact structure rather than full packaging integration.

The strongest single pattern in this dataset is a co-filing relationship between Tokyo Electron's parent entity and its US holding company, which together appear on five of the thirteen tracked families. TSMC, Applied Materials and Huawei also appear among the ranked assignees, covering foundry, equipment and device-maker perspectives respectively. All of the leading assignees show zero or negative filing momentum in the most recent tracked year, though this likely reflects publication lag rather than an actual slowdown.

With only 13 published families across an 11-year search window, this is not a crowded field by any conventional measure. Filing activity peaked once, in 2020, and has not sustained since, with the 2022 midpoint showing no filings at all. That combination — low absolute volume and a stalled trend — suggests meaningful claim space remains open, particularly outside the core device-structure classifications where most existing filings sit.

EP4791148A1, filed by Huawei Technologies, claims a CFET structure where a first transistor sits on one level and a second transistor on a level stacked above it, with the two transistors' channels offset from each other while still maintaining partial overlap. That specific geometric relationship — offset-but-overlapping channels across stacked levels — is the novel element rather than vertical stacking generally, which is already the baseline CFET concept. Anyone designing a stacked-channel CFET architecture should check where their channel alignment falls relative to this claim before finalising a layout.

The classification data points to logic-cell-level topology as the clearest gap: only three of thirteen families touch H03K, the logic-circuit classification, meaning most existing claims stop at the device or contact level rather than extending to specific standard-cell layouts built from CFET stacks. Backside power rail contact schemes and hybrid-bonding alignment tolerance methods also show little dedicated coverage in this corpus. A first claim in these areas would need to tie the structural CFET arrangement to a specific circuit-level or process-tolerance outcome to differentiate from the existing structural filings.