CFET Doping & Implantation Patents: Leaders, Trends & White Space 2026
- Small, concentrated field. only 21 patent families sit at the intersection of CFET structures and ion implantation, conformal doping or dopant activation claims — this is still a narrow, contestable corner of transistor IP.
- Filing has not accelerated. activity peaked at 4 families in 2020 and has since flattened, with no assignee showing fresh momentum in the latest recorded year.
- Almost entirely US-anchored. 20 of 21 records were filed through the USPTO against a single PCT filing, meaning the enforceable rights here are concentrated in one jurisdiction.
Filing growth compares 2021 (4 records) with 2024 (4) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this landscape covers
Complementary FET (CFET) devices stack n-type and p-type channels vertically, and building them requires doping and activation steps that differ sharply from planar or even FinFET flows. This landscape isolates patent families that combine explicit CFET or complementary field-effect transistor claim language with junction-engineering terms — ion implantation, conformal doping, dopant activation — inside the IPC classes covering semiconductor device fabrication (H01L21/265, H01L21/2255) and device structure (H01L29/66).
The result is a tightly scoped set: 21 families total, almost all filed in the United States, spanning a filing window with no sustained upward trend. That scarcity is itself the finding — this is a specific fabrication problem, not yet a broad claiming battleground.
Filing trend and technology composition
Annual filing counts and IPC distribution for the 21 families in this landscape, drawn directly from the underlying search.
A flat filing curve, not a rising one
Filings sat at zero in 2017, rose to a peak of 4 in 2020, and by the 2022 midpoint had settled to 3 — evidence of a technology area that opened, got a handful of claims staked, and has not since attracted a wave of new entrants. Because publication lags filing by roughly 18 months, the most recent year understates true activity, but even accounting for that lag the mid-period plateau is real.
Concentrated in two device classes
Every record classifies under H01L (semiconductor devices generally), and 15 of the 21 also fall under H10D, the newer subclass specifically covering semiconductor device structures — a strong signal that examiners and applicants alike treat these as core device-architecture claims rather than peripheral process tweaks.
Shares are the percentage of the 21 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Complementary FET Doping and Implantation with Eureka
This page is one run against one query. Ask Eureka your own question about complementary fet doping and implantation and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art
CFET buried sidewall contact with spacer foot
A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region.Filed by International Business Machines Corporation, published 2023-03-02.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20210265345A1 | Stacked Nanosheet CFET with Gate All Around Structure | 77 |
| 2 | US20210265348A1 | Stacked field effect transistor with wrap-around contacts | 51 |
| 3 | US11177258B2 | Stacked nanosheet CFET with gate all around structure | 21 |
| 4 | US5192698A | Making staggered complementary heterostructure FET | 19 |
| 5 | US6054729A | Gallium antimonide complementary HFET | 18 |
| 6 | US20130164891A1 | High density butted junction CMOS inverter, and making and layout of same | 12 |
| 7 | US20220052047A1 | Stacked field effect transistor with wrap-around contacts | 11 |
| 8 | US11201153B2 | Stacked field effect transistor with wrap-around contacts | 11 |
| 9 | US20230411358A1 | Method and structure of forming independent contact for staggered cfet | 7 |
| 10 | US6384432B1 | Gallium antimonide complementary HFET | 6 |
Citation counts reflect influence within the searched corpus and favour older filings; treat them as a map of foundational art, not a ranking of current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three read-throughs from the trend, classification and citation data above.
The wave has already crested
Peak activity was 2020 at 4 families, with the 2022 midpoint already down to 3 and the latest recorded year back at zero. A flat or declining curve after an early peak usually means the foundational architecture claims are staked and later entrants are working around them rather than filing fresh core IP.
Device-structure claims dominate over process claims
Every record sits in H01L, but the majority also carry the newer H10D device-structure classification, which points to claims written around the physical stack — channel isolators, source/drain regions, contact geometry — rather than generic implantation process steps.
Foundational GAA nanosheet claims carry the most weight
The most-cited records describe stacked nanosheet CFET structures with gate-all-around geometry and wrap-around contacts — these are the citations a freedom-to-operate search in this space will keep surfacing, regardless of filing date.
Rights are concentrated in one jurisdiction
Only a single PCT filing sits alongside 20 US filings. A design team operating outside the US should not assume freedom to operate simply because a family has not been extended there yet.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to complementary fet doping and implantation, with the prior art for and against each one.
Who holds the ground
With only 21 families in the set, this is a landscape of a handful of assignees rather than a crowded field. Momentum has stalled across the board: none of the tracked assignees show filings in the latest recorded year, which is consistent with the overall flat trend rather than a single company pulling back.
Almost no joint filing
The single co-assignee pair in this dataset links two IBM entities across jurisdictions, not two independent companies. There is essentially no evidence of cross-company collaboration in this specific claim space.
A stalled field, not a growing one
Major device makers and a national research institute all show zero filings in the most recent recorded year. Combined with the 2020 peak, this suggests the core architectural claims in this niche were largely staked in the late 2010s and early 2020s.
A small set, worth watching closely
Because the total family count is small, a single new entrant filing two or three families could visibly shift the ranking. Competitive monitoring here is cheaper and more tractable than in high-volume CFET architecture searches generally.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | — |
| TRW Inc. (USA) | 0 | — |
| Texas Instruments Incorporated | 0 | — |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | — |
| Electronics and Telecommunications Research Institute (ETRI) | 0 | — |
| Intel Corporation | 0 | — |
| International Business Machines (China) Co., Ltd. | 0 | — |
| United States of America, as represented by the Secretary of the Air Force | 0 | — |
Where to take this analysis
This landscape is a starting map, not a freedom-to-operate opinion. The next steps depend on whether you are filing, designing around, or scouting for acquisition targets.
Run a full-text claim comparison
Pull the independent claims of the highest-cited records and map them against your own process flow before drafting, especially around source/drain isolation and buried contact geometry.
Open Eureka →Track the assignees with zero recent filings
A stalled filer can restart quickly once a fabrication node matures. Set an alert on the assignees in this set rather than assuming the plateau is permanent.
Open Eureka →Check the under-claimed branches
The gate chips above point to specific junction-engineering steps with thin coverage. Validate novelty there before assuming the space is closed.
Open Eureka →Common questions on CFET doping and implantation IP
This landscape identifies 21 patent families that combine explicit complementary FET (CFET) claim language with junction-engineering terms such as ion implantation, conformal doping or dopant activation, within the relevant semiconductor device IPC classes. That is a small set compared to CFET architecture patents broadly, because most CFET filings describe the stacked channel structure without claiming the doping process in detail. Anyone running a broader keyword search will find far more CFET-related filings; this figure is specific to the doping and implantation intersection.
International Business Machines Corporation appears as the most consistent filer in this set, including the single co-assignee pairing across its own entities in different jurisdictions. Other named parties include Texas Instruments, TSMC, Intel and a Korean national research institute, but none of these show filings in the most recent recorded year. With only 21 families total, rankings here can shift with a small number of new filings, so treat any single leader as provisional rather than entrenched.
Not currently. Filing activity peaked at 4 families in 2020, had already fallen to 3 by the 2022 midpoint, and shows no filings from any tracked assignee in the latest recorded year. Because publication typically lags filing by around 18 months, the most recent year is always undercounted, but the mid-period plateau suggests the core architectural claims were staked early rather than the field still expanding. This looks more like a settled niche than an emerging one, at least based on the filings captured so far.
H01L is the long-standing IPC subclass covering semiconductor devices broadly, and every record in this landscape falls under it. H10D is a newer, more specific subclass for semiconductor device structures, and 15 of the 21 families also carry it, indicating claims drafted around the physical device architecture — channel isolators, source/drain stacking, contact placement — rather than generic fabrication process steps. A filing that only carries H01L without H10D is more likely to be a process-only claim, which can be a useful quick filter when triaging results.
Based on the classification and filing pattern in this set, sub-areas such as selective bottom source/drain dopant activation sequencing, doping uniformity control across stacked nanosheet channels, buried contact dopant diffusion barriers, and independent threshold-voltage tuning via implant dose for top versus bottom devices show little dedicated claim coverage. That does not guarantee novelty — it means this specific search did not surface dense prior art there. A proper freedom-to-operate check should still be run against the full CFET architecture literature, not just this doping-focused subset, before relying on any of these branches as open.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.