A complementary FET (CFET) stacks a PMOS transistor directly above an NMOS transistor in the same vertical footprint, and the gate dielectric — the high-k layer plus its interfacial layer — has to be formed and tuned separately for both channels within that stack. This is mechanically and chemically harder than a planar or single-tier gate stack because the top and bottom devices need different threshold-voltage tuning, often via dipole engineering, while sharing a fabrication sequence. Patent claims in this niche typically combine a CFET structural element (stacking, gate-all-around wrap, channel material) with a specific dielectric formation or treatment step, which is why the search here layers CFET terminology against gate-dielectric and interfacial-layer language rather than searching either alone.

The ranking in this dataset is led by major foundries and integrated device manufacturers, with Taiwan Semiconductor Manufacturing Company holding the representative recent grant covering a supercritical-fluid dielectric treatment step. IBM, Intel, Qualcomm and equipment suppliers such as Applied Materials and Tokyo Electron also appear among the top filers. None of the leading assignees show filing activity in the most recent tracked year in this corpus, though that is consistent with the roughly eighteen-month publication lag rather than necessarily reflecting an actual stop in filing.

Not by the numbers in this dataset. Filing peaked at 26 families in 2023 and had fallen back toward the 2022 level of 14 by the following year's midpoint, which reads as a flattening or mild decline rather than continued growth. Some of that apparent drop-off is an artefact of publication lag understating the most recent one to two years, so the true picture will only be clear once later filings finish publishing — but even accounting for lag, the trajectory looks like a completed initial claiming wave rather than an accelerating one.

The thinnest claim density relative to the core structural patents sits in dipole-engineering dielectric tuning for independently setting top and bottom channel thresholds, interfacial-layer composition specific to stacked geometries, and post-formation treatments such as supercritical-fluid processing of the high-k layer. Reliability of the gate dielectric under the thermal budget imposed by sequential deck processing is another area with comparatively few dedicated claims. Because the overall corpus is small — 85 families — any of these branches could still be claimed broadly by a well-drafted first filing.

US12218225B1 claims a specific sequence — forming a gate dielectric layer wrapping around top-region channels, then treating it with radicals in a supercritical fluid, then forming the metal gate — assigned to Taiwan Semiconductor Manufacturing Company. It does not broadly block gate dielectric formation or treatment in CFET structures generally; it blocks that particular supercritical-fluid radical-treatment sequence applied to a top-channel wrap-around dielectric. Alternative treatment chemistries, different treatment ordering, or treatments applied to the bottom-channel dielectric instead would need their own freedom-to-operate review against this and the other most-cited structural patents in the corpus.