A complementary FET (CFET) stacks an NMOS transistor directly above a PMOS transistor in the same device footprint, enabling logic cell areas well below what lateral FinFET or nanosheet architectures can reach. The gate dielectric — typically a hafnium-based high-k film grown over a thin silicon-oxide interfacial layer — must wrap around both the upper and lower channel nanosheets simultaneously, which means a single deposition sequence has to satisfy the threshold-voltage, leakage, and reliability requirements of two complementary devices at once. That constraint makes the dielectric process the most tightly controlled module in the CFET integration flow, and it explains why gate-dielectric patent filings have grown proportionally faster than any other CFET process sub-domain.

The corpus of 85 families is concentrated at the top: a small group of integrated device manufacturers and advanced-process equipment companies accounts for the majority of families. Taiwan Semiconductor Manufacturing Company leads by family count, with a portfolio skewed toward post-formation dielectric quality improvement. IBM files through both its US and China entities and covers the process-to-device spectrum. Tokyo Electron, as a leading ALD and CVD tool supplier, contributes families at the intersection of tool design and process chemistry. A long tail of single-family entrants — including fabless designers and research institutions — rounds out the corpus, but none holds enough families individually to constitute a blocking position on its own.

The densest prior art sits on broadly stated ALD-deposited hafnium-based high-k films and their classical thermal anneal treatments. Sub-areas with notably thin coverage include supercritical-fluid or radical-based repair of the bottom-channel dielectric specifically (as distinct from the top channel), selective interfacial-layer regrowth after gate etch, dipole-engineering approaches targeting dual-threshold CFET cells in a single process step, and memory-device extensions of logic CFET dielectric flows. Geographically, the EPO and PCT filing space is thin — only 5 families each — making non-US jurisdictions an underexplored avenue for building portfolio leverage.

Within the CFET technology space overall, the high-k gate dielectric sub-domain is one of the more active process clusters, reflecting the centrality of the dielectric stack to device performance. The 85 families indexed here peaked in 2023 at 26 annual filings, a level consistent with the broader CFET filing surge that accompanied the industry's move from research demonstrations to pilot-line integration. The subsequent plateau suggests that the most obvious claim structures — composition, deposition method, basic interfacial-layer control — are now occupied, and that new entrants must differentiate on process variants, specific material combinations, or novel treatment steps to obtain broad independent claims.

US12218225B1 describes and claims a method in which a gate dielectric layer — formed over and wrapping around the top-channel nanosheets of a CFET structure — is subjected to a radical treatment while the structure is immersed in a supercritical fluid, followed by metal gate electrode formation. The supercritical-fluid medium allows radical species to penetrate and repair the dielectric without the high thermal budgets that would disturb previously formed metal-gate or epitaxial layers. For competitors, this patent narrows the freedom to use supercritical-fluid environments for post-deposition dielectric treatment in CFET flows; design-around options would likely require either a different treatment medium, a fundamentally different radical-generation mechanism, or a process sequence in which the dielectric is treated before the top-channel structure is fully formed. IP counsel should review the issued claims carefully before drawing conclusions about scope.

Dipole engineering refers to the deliberate insertion of a thin metal-oxide layer — typically lanthanum oxide for NMOS or aluminium oxide for PMOS — between the high-k dielectric and the interfacial silicon oxide. The inserted layer creates an electrostatic dipole at the interface that shifts the effective work function and therefore the threshold voltage of the transistor, enabling threshold-voltage tuning without changing the metal gate material. In a CFET, where the top and bottom transistors require different threshold voltages, selective dipole insertion is an attractive approach because it can in principle be achieved through selective deposition or etch-back steps on a stacked structure. The current corpus contains families touching dipole engineering, but this sub-area is less densely claimed than bulk high-k composition or interfacial-layer thickness control — making it one of the more accessible areas for new filings with genuinely novel process sequences.