A CFET stacks an n-type and a p-type transistor vertically within the same footprint, which lets a logic cell shrink without shrinking the transistors themselves. That vertical stacking pushes new demands onto the interconnect and power delivery layers, because signal and power routing now have to reach both the top and bottom device without adding parasitic resistance or shorting the stack. Patent activity in this space concentrates on buried power rails, backside power delivery and via structures precisely because those are the parts of the design that break first when devices go vertical.

The tracked assignees span foundry equipment suppliers, IDMs and a semiconductor research consortium, reflecting how CFET interconnect work spans both device fabrication and process equipment. None of the named assignees show active filing in the most recent tracked year, though this likely reflects publication lag rather than an actual pullback. A single co-assignee pairing — between a semiconductor equipment maker and its US holding entity — is the only strong collaboration signal in the dataset.

The filing trend in this dataset peaked at six families in 2023, up from a midpoint of three in 2022, and has not exceeded that since. Because publication typically lags filing by around 18 months, the most recent years will likely revise upward as more applications clear the pipeline, so it's premature to call this a definitive peak. What the data does support is that the density of foundational structural claims — buried rails, backside contacts — was highest around 2022-2023.

The thinner claim density sits around single-damascene via processing for parasitic resistance reduction, independent gate contact schemes, and claims that tie interconnect structure directly to logic-cell circuit behaviour. These sit in the same IPC classes as the dominant buried-power-rail and backside-contact claims but have far less citation and filing depth behind them. A first claim in these areas would likely need to specify a concrete process sequence or circuit-level effect rather than a general structural arrangement, since the broad structural language is already well covered.

The United States receiving office accounts for the majority of tracked records, far ahead of WIPO PCT filings and EPO filings combined, with a single Singapore record rounding out the set. That concentration means a freedom-to-operate review for CFET interconnect work should start with US prior art and only then expand outward. It also means assignees have not yet broadly pursued multi-jurisdiction protection specifically for these interconnect claims, which may itself be a gap worth watching.