A CFET stacks an n-type and p-type transistor vertically within the same footprint, instead of placing them side by side as conventional planar CMOS does. This vertical arrangement is aimed at reducing cell height and standard-cell area once lateral gate-pitch scaling becomes uneconomical. The patents in this landscape focus specifically on the fabrication and integration methods that make that stacking work in practice, including channel-material choice, thermal-budget sequencing during upper-tier processing, and power-delivery routing around the stacked pair.

The tracked dataset covers 29 patent families total, filed by a short list of assignees spanning IDMs, a fabless designer, process-equipment suppliers and a research consortium. Only two co-assignee relationships appear across the whole set, meaning most of these families were filed by a single entity rather than jointly. That is a small, still-forming field rather than a mature one with dozens of established players.

It is accelerating. Filings moved from zero in 2017 to just one at the 2022 midpoint, then jumped to a peak of 9 in 2023. Because patent publication typically lags filing by around 18 months, the apparent dip in the most recent years is very likely a reporting artifact rather than a real slowdown — the underlying filing rate has probably kept climbing.

EP4576188A1, filed by IMEC VZW, claims a CFET structure with a lower transistor, an upper transistor carrying a source/drain structure, a power rail positioned below the lower transistor, and a power routing line above the upper transistor that connects to that source/drain structure. It is specific to that particular power-delivery arrangement around a stacked pair, not to CFET stacking in general, so it constrains that one routing topology rather than the whole architecture. Anyone designing power delivery for a stacked CFET cell should check this claim set before committing to a similar rail-above/rail-below layout.

The most-cited existing records cluster around multiple-channel-material integration and basic 3D stacking architecture, which means those specific claim territories are comparatively crowded. Thinner coverage appears around sequential low-thermal-budget processing for upper-tier transistors, source/drain epitaxy tuned for stacked n-type/p-type pairs, and power-rail routing variants beyond the one IMEC has claimed. These are reasonable areas to search closely before drafting a new application, given how few total families exist to block them.