A complementary FET stacks an n-type and a p-type transistor vertically on top of each other rather than placing them side by side, which lets a chip pack both device types into roughly the footprint of one. That vertical sharing means the two devices can share gate stack, contact and thermal paths, so stress mechanisms like bias temperature instability and hot-carrier degradation can couple between the top and bottom device in ways that do not happen in planar or lateral gate-all-around designs. Reliability engineering for CFETs therefore has to account for interactions between tiers, not just degradation within a single device, which is why reliability-specific claim language is only now starting to appear as a distinct category in filings.

This landscape identifies 13 published patent families that combine CFET or complementary field-effect transistor terminology with reliability-specific claim language such as bias temperature instability, TDDB reliability, hot carrier degradation or device reliability. That is a small number for a semiconductor topic, and it reflects a narrow search intersection rather than the full body of CFET fabrication patents, which is considerably larger. Most CFET-related filings still address structure and process, not reliability mechanisms, as a primary claim focus.

The recent-year momentum data shows several major semiconductor players — including a leading foundry, an IDM with a related domestic entity, a fabless chip designer and consumer-electronics manufacturers — with filings in this set, but none currently shows growth in the latest tracked year. No single assignee has established a clear lead by volume in this specific reliability-claim intersection. That flat momentum across all named filers is itself a signal: the space has not yet consolidated around one or two dominant players, which is unusual for a semiconductor reliability topic this far into CFET's development.

The clearest gaps sit around vertical-stack-specific degradation mechanisms rather than mechanisms inherited from planar devices: modelling TDDB across a shared vertical dielectric stack, isolating hot-carrier effects when top and bottom devices share a gate structure, and balancing n and p drive current specifically under bias-temperature stress. The IPC composition also shows only single-family reach into nanotechnology-adjacent classifications, suggesting materials-level reliability claims (such as 2D dielectric approaches) are still lightly claimed. A first claim in these areas would need to tie a specific stacked-device geometry to a specific measurable degradation or leakage outcome, rather than claiming reliability improvement in the abstract.

Thirteen families is enough to see structural patterns — filing timing, receiving-office spread, IPC concentration — but too few to draw firm conclusions about market share or competitive intent. Publication lag of roughly 18 months also means the most recent year or two in this dataset understates real filing activity, since many 2025–2026 filings will not have published yet. Treat this landscape as a directional map of where reliability-specific CFET claims currently sit, and re-check it periodically as more of the pipeline publishes.