A CFET stacks an NFET and a PFET transistor vertically within a single device footprint, rather than placing them side by side as in conventional CMOS. This is done through either monolithic integration, where both tiers are built in one continuous process flow, or sequential integration, where the bottom tier is completed before the top tier is added. The patent evidence in this landscape centres on the process details that make this stacking manufacturable: dielectric isolation in the gate cut, source/drain contact schemes, self-heating mitigation and epitaxy alignment between the two tiers.

The ranking covers 8 companies in total, counted in patent records, with the leading assignee holding 12 records and the fifth-placed company holding 2. This is a full ranking rather than a top-50 or top-100 cut, and most of the eight companies file only a handful of records each, so the field has one clear leader followed by a long tail of lighter filers. Recent-year data shows the historical leader with zero filings in the latest year, while a different company logged the field's only filing so far in that period.

Filing activity was essentially flat through 2017-2021 before rising, and the busiest year recorded so far is 2023, with 15 records. Counts for the most recent year are necessarily partial because patent publication typically lags the actual filing date by around 18 months, so the true 2025-2026 filing volume is understated in any dataset pulled today. Readers should treat any apparent recent decline with that lag in mind rather than as evidence of cooling interest.

US20240203990A1 describes a CFET device with a first transistor stacked under a second transistor, where the gate cut adjacent to the stack uses two different dielectric materials chosen to apply distinct stress to each transistor's channel. This lets the NFET and PFET in the same stack have their electrical performance tuned independently through material choice alone, rather than through separate process steps for each device. Anyone designing a gate-cut isolation scheme for a stacked NFET/PFET pair should check this claim structure closely, since it covers a specific and commercially relevant mechanism for tuning stacked-device performance.

The IPC composition shows heavy concentration in general semiconductor device classes (H01L at 63.6% and H10D at 45.5% of the 33 records in scope), while adjacent classes such as memory device manufacture, digital data processing, electron tubes, and implant or body-fluid devices each sit at only 3.0%-9.1% of records. That gap suggests core stacking, isolation and contact architecture is well claimed, while integration of CFET structures into memory arrays, biomedical devices or passive-diode co-integration remains comparatively open. A first claim in one of these thinner branches would likely need to tie the CFET stack's specific geometry to the adjacent application rather than restate the base architecture.