CFET Thin Film Deposition Patents: Leaders & White Space 2026
- Filing has gone flat, not up. activity peaked at 7 families in 2020, and the 2022 midpoint sits at the same level — this is a plateaued field, not a rising one.
- Citations concentrate on stacked nanosheet gate-all-around structures. the two most-cited records both describe stacked CFET architectures with gate-all-around and wrap-around contacts, filed years apart from the rest of the corpus.
- No assignee shows recent momentum. every tracked assignee — from IBM to Applied Materials to TSMC — logs zero filings in the latest year, consistent with the ~18-month publication lag rather than a slowdown in R&D.
Filing growth compares 2021 (6 records) with 2024 (4) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this landscape covers
This dataset tracks patent families at the intersection of complementary FET (CFET) device architectures and thin film deposition methods — atomic layer deposition, chemical vapor deposition, epitaxy — filtered to IPC classes covering deposition equipment, general semiconductor devices, and crystal growth. The search string ties CFET terminology directly to deposition-process language in the claims or description, so it captures process integration work rather than device claims alone. At 34 families, this is a narrow, technically specific corner of semiconductor patenting, not a broad device category.
Coverage runs from 2015 through the 2026 cut-off. Because publication lags filing by roughly 18 months, the last one to two years in any trend chart will always look thinner than they eventually turn out to be.
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Filing trend and technology composition
34 published families sit across eight IPC subclasses, with filings clustering in a small number of years rather than climbing steadily.
A flat curve since the 2020 peak
Filings rose to a peak of 7 in 2020, and the 2022 midpoint holds at the same 7-family level — there is no clear upward or downward slope once the recency lag is accounted for. Read this as a technology area that reached a stable filing rate early rather than one still ramping.
Concentrated in H01L and H10D
H01L (semiconductor devices) covers 33 of the 34 records and H10D (general semiconductor devices) covers 21 — the two subclasses most directly tied to CFET device structure. Smaller counts in H10P, G05F, H03K, H10W, B82Y and B23K mark adjacent circuit-control and nanotechnology-application angles that are touched on but not built out.
Shares are the percentage of the 34 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Complementary FET Thin Film Deposition with Eureka
This page is one run against one query. Ask Eureka your own question about complementary fet thin film deposition and every answer comes back with the patent numbers behind it.
Try EurekaThe records other filings cite most
Tunneling field effect transistors and transistor circuitry employing same
A p-channel tunneling field effect transistor (TFET) built from either group IV or group III-V multi-layer structures, paired with an n-channel TFET using a p-type delta-doped region between n-type and p-type zones, forming complementary TFET circuitry.US9941117B2 — Ohio State Innovation Foundation — filed 2018-04-10
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20210265345A1 | Stacked Nanosheet CFET with Gate All Around Structure | 77 |
| 2 | US20210265348A1 | Stacked field effect transistor with wrap-around contacts | 51 |
| 3 | US20230178435A1 | Complementary FET (CFET) devices and methods | 21 |
| 4 | US11177258B2 | Stacked nanosheet CFET with gate all around structure | 21 |
| 5 | US6054729A | Gallium antimonide complementary HFET | 18 |
| 6 | US20230326925A1 | Monolithic complementary field-effect transistors having carbon-doped release layers | 17 |
| 7 | US20230125316A1 | CFET with independent gate control and low parasitic capacitance | 14 |
| 8 | US20220052047A1 | Stacked field effect transistor with wrap-around contacts | 11 |
| 9 | US11201153B2 | Stacked field effect transistor with wrap-around contacts | 11 |
| 10 | US20230017350A1 | Independent gate contacts for cfet | 8 |
Citation counts are drawn from a searched corpus and skew toward older filings — treat them as a measure of influence on later drafting, not of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the evidence actually shows
Three patterns stand out once the ranking and trend data are read together: a small set of highly-cited architecture patents, a technology base that has not grown since 2020, and receiving-office activity that stays heavily US-centred.
Two stacked-nanosheet filings anchor the field
US20210265345A1 and US20210265348A1, both describing stacked nanosheet CFET structures with gate-all-around geometry, carry the highest citation counts in the corpus by a wide margin over the rest of the ranking.
No growth since the 2020 peak
The 2022 midpoint matches the 2020 peak at 7 families, and 2017 opens at zero. This is a filing curve that rose and plateaued rather than one still accelerating.
Filing is US-centred with a thin PCT layer
26 of the tracked records route through the United States, with 5 filed via WIPO/PCT and small counts in Taiwan and China. That leaves limited visibility into any parallel Chinese-language filing strategy outside this corpus.
Co-filing is rare in this dataset
Only one co-assignee pairing appears across the 34 families, between Tokyo Electron entities. Most filings in this space are single-assignee, which limits what co-filing patterns alone can tell you about alliance structure.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to complementary fet thin film deposition, with the prior art for and against each one.
Who is active, and where the gate stands open
The named assignees span foundries, equipment makers and a university foundation, but none show filings in the latest tracked year — a pattern consistent with publication lag rather than exit from the field.
Everyone shows zero in the most recent year
IBM, Applied Materials, TSMC, Tokyo Electron, Ohio State University and TRW all register zero filings in the latest tracked year, and Applied Materials shows a -100% YoY change. Given the ~18-month publication lag, this says more about the data cut-off than about a stalled research pipeline.
Foundries and equipment makers both hold ground
The assignee set mixes device/foundry players (TSMC, IBM) with deposition equipment specialists (Applied Materials, Tokyo Electron), reflecting that this search sits deliberately at the seam between CFET device claims and the deposition processes used to build them.
Ohio State supplies the representative filing
Ohio State Innovation Foundation is the only university-affiliated assignee named among the tracked filers, and its representative record (US9941117B2) predates most of the stacked-nanosheet activity that later drew the heaviest citations.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | — |
| Applied Materials, Inc. | 0 | -100% |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | — |
| Tokyo Electron Limited | 0 | — |
| The Ohio State University | 0 | — |
| TRW Inc. (U.S.) | 0 | — |
| Qualcomm Incorporated | 0 | — |
| Tokyo Electron U.S. Holdings, Inc. | 0 | — |
Where to take this
The numbers above tell you where claims already sit. The next step is checking how a specific process or architecture idea reads against them.
Map a candidate process against the cited core
Run a specific deposition sequence or channel material against the two dominant stacked-nanosheet filings before drafting, since most later citations trace back to that pair.
Explore in Patsnap Eureka →Track the recency lag directly
Re-pull the 2024–2026 filing counts periodically — the flat trend recorded here will fill in as later publications land.
Explore in Patsnap Eureka →Check the white-space chips against your own claims
The under-claimed sub-areas listed here are starting points, not conclusions — verify freedom-to-operate on any specific claim language before relying on thin coverage.
Explore in Patsnap Eureka →Common questions about CFET deposition patents
A complementary FET stacks an n-type and p-type transistor vertically in the same footprint, rather than placing them side by side as in conventional CMOS. Building that stack requires precise thin film deposition — atomic layer deposition, chemical vapor deposition, and epitaxy — to form the channel layers, gate-all-around structures, and inter-tier isolation without disturbing layers already in place. That is why patent filings in this space tie CFET device claims directly to specific deposition process steps rather than treating architecture and process separately.
The named assignees in this dataset include foundries and device makers such as IBM and TSMC, deposition equipment specialists such as Applied Materials and Tokyo Electron, and at least one university group, Ohio State Innovation Foundation. None of these assignees show filings in the latest tracked year, which reflects the roughly 18-month lag between filing and publication rather than reduced activity. The corpus itself is small — 34 families — so leadership here is better read as technical influence than as filing volume.
No — the filing trend is flat rather than rising. Activity peaked at 7 families in 2020, and the 2022 midpoint sits at the same level, with 2017 opening at zero. Combined with the publication lag affecting the most recent years, this points to a technology area that reached a stable filing rate several years ago rather than one still accelerating.
US9941117B2, assigned to Ohio State Innovation Foundation and filed in 2018, claims complementary tunneling field-effect transistor (TFET) circuitry built from group IV or group III-V multi-layer structures, with a p-type delta-doped junction region in the n-channel device. It is a device-and-materials claim rather than a deposition-process claim, so it constrains channel material and doping-profile choices for tunneling-FET-style complementary circuits specifically, not CFET deposition sequencing in general. Anyone working with delta-doped III-V or SiGe channel regions in a tunneling FET context should read its claims closely before finalizing a doping profile.
The densest claim coverage sits in H01L and H10D — core CFET device structure — while adjacent process areas such as group III-V epitaxial channel integration, ALD-based inter-tier isolation, and wrap-around contact metallization sequencing show thinner coverage in this corpus. That does not guarantee those areas are open; it means fewer filings in this specific dataset touch them, so a freedom-to-operate check against the broader patent universe is still necessary before relying on the gap.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.