Complementary FET Patents: Who Leads, Where the Gaps Are 2026
- Small, concentrated field. Only 41 patent families exist worldwide across the stacked nFET/pFET architecture search, with filing peaking at 23 in 2023 and no clear year-on-year growth trend before that.
- US-centred filing. 18 of the tracked records entered via the United States receiving office, ahead of Europe (9) and the WIPO/PCT route (8), with China, Germany and India each in single digits.
- Most cited work is process-focused, not device-only. The highest-cited record concerns sequential 3D logic fabrication temperature control rather than the transistor stack itself, suggesting integration process claims currently carry more weight than architecture claims alone.
Filing growth compares 2021 (8 records) with 2024 (5) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What the CFET patent record actually shows
Complementary FET (CFET) architecture stacks an nFET directly over a pFET within a single footprint, and the patent record around it is still small relative to mainstream transistor technologies. Across the tracked window, 41 patent families match a search built around stacked nFET/pFET architecture, monolithic CFET, and sequential CFET claim language, filtered to the semiconductor-device IPC classes most relevant to gate and junction structure. That is a narrow, still-forming field rather than a mature one, and filing activity reflects it: growth from 2017 was effectively flat until a peak in 2023 at 23 filings, with no single year since showing sustained acceleration.
Because publication typically lags filing by around 18 months, the most recent years in any CFET trend chart will understate real filing activity — 2025 and 2026 figures should be read as provisional, not as a slowdown.
Let an AI agent run this analysis on your own technology
Pick a task. Every answer cites the patents behind it.
Filing trends and technology composition
The IPC spread and receiving-office mix point to a technology still concentrated in a handful of jurisdictions and a handful of adjacent subclasses, rather than one spread widely across the semiconductor stack.
A flat-to-declining filing curve after a 2023 peak
Filings were at zero as recently as 2017, rose gradually, and peaked at 23 in 2023; the 2022 midpoint of 5 shows the field was still small just before that peak, and later years show no confirmed continuation of growth once publication lag is accounted for.
H01L dominates, with H10D and H10W as the next tier
Every tracked record sits under H01L (semiconductor devices), and a meaningful secondary cluster sits in H10D (general semiconductor devices, 9 records) and H10W (7 records); single records touching welding/soldering (B23K), pulse/logic circuits (H03K) and memory device manufacture (H10B) mark the outer edge of where CFET claims currently reach.
Shares are the percentage of the 41 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Complementary FET Transistor Architecture with Eureka
This page is one run against one query. Ask Eureka your own question about complementary fet transistor architecture and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this dataset
Monolithic 3D CFET circuits and manufacturing methods (EP4569539A1)
Filed by QUALCOMM INCORPORATED and published 2025-06-18, this record describes monolithic three-dimensional complementary field-effect transistor circuits together with their manufacturing method — squarely inside the monolithic CFET branch of this landscape.Representative of the monolithic (single-tier, sequentially processed) CFET filing route rather than the sequential-wafer-bonding alternative.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20220122892A1 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal … | 26 |
| 2 | US20230178435A1 | Complementary FET (CFET) devices and methods | 21 |
| 3 | US20230377998A1 | Method of forming confined growth s/d contact with selective deposition of inner spacer for cfet | 19 |
| 4 | US20230326925A1 | Monolithic complementary field-effect transistors having carbon-doped release layers | 17 |
| 5 | US20250048690A1 | A complementary field-effect transistor device | 14 |
| 6 | US20230178554A1 | Complementary Field-Effect Transistor Device | 11 |
| 7 | US20240047455A1 | Monolithic three-dimensional (3D) complementary field effect transistor (CFET) circuits and method of manufac… | 11 |
| 8 | US20240222429A1 | Semiconductor device structure and methods of forming the same | 9 |
| 9 | US20240321646A1 | Threshold voltage tuning using a multiple dipole loop process for CFET devices | 5 |
| 10 | CN115132727A | 半导体结构及其形成方法 | 4 |
Citation counts are drawn from the searched corpus only and favour older filings; treat them as a signal of influence within this dataset, not as a current-importance ranking.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the citation and filing pattern signals
Reading the top-cited records alongside the filing curve suggests process integration, not the basic stacked-transistor concept, is where current CFET patent value concentrates.
Process sequencing outranks pure architecture claims
The single most-cited record in this dataset claims a method for sequentially decreasing processing temperature during 3D logic fabrication — a thermal-budget process claim, not a transistor-stack architecture claim. That it leads the citation table suggests integration-process patents are proving more foundational, or at least more frequently referenced, than device-geometry patents alone.
A short, sharp filing peak rather than sustained growth
Filing rose from zero in 2017 to a peak of 23 in 2023, roughly quadruple the 2022 midpoint of 5. A single peak year followed by a flatter trend is more consistent with a wave of early architecture claims being staked out than with an industry still in an accelerating filing race.
US filing dominance, with PCT as the main alternate route
Eighteen of the 41 tracked families entered via the United States receiving office, more than double the next-largest single office (EPO, 9). The WIPO/PCT route accounts for 8 families, indicating many applicants are keeping options open for later national-phase entry rather than filing directly in multiple jurisdictions.
Collaboration is rare and mostly regional
Only three co-assignee pairings appear in the dataset, the strongest linking an inter-university microelectronics centre with a Chinese telecoms equipment maker. Co-filing is not yet a common strategy in this niche — most families carry a single assignee.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to complementary fet transistor architecture, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Interuniversity Microelectronics Centre (IMEC) | Huawei Technologies Co., Ltd. | 3 |
| Tokyo Electron Limited | Tokyo Electron U.S. Holdings, Inc. | 1 |
| Semiconductor Manufacturing International (Beijing) Corporation (SMIC Beijing) | Semiconductor Manufacturing International (Shanghai) Corporation (SMIC Shanghai) | 1 |
With only three co-assignee pairs identified and the strongest at just 3 shared filings, CFET patenting so far looks like largely independent corporate R&D rather than joint-venture-driven filing.
Who is filing, and how recently
The named assignees span foundries, IDMs, equipment suppliers and a university-linked microelectronics centre, but recent-year momentum is muted across the board — every listed assignee shows zero filings in the latest tracked year, consistent with publication lag rather than a genuine pullback.
Foundries and IDMs anchor the field
The assignee list is dominated by large-scale chipmakers and foundries rather than fabless design houses, matching the process-heavy, integration-focused nature of CFET claims seen in the citation leaders.
Equipment and tooling players sit close behind device makers
Semiconductor equipment suppliers appear among the tracked assignees, reflecting that CFET's tight nFET/pFET stacking depends as much on deposition and etch tooling claims as on the transistor geometry itself.
Cross-border collaboration is the exception
The one multi-filing co-assignee pair spans an inter-university microelectronics centre and a major Chinese telecoms equipment maker; other pairs link a Japanese equipment group with its US holding entity, and a Chinese foundry with its own subsidiary — internal or regional links, not broad industry alliances.
| Assignee | Recent year | YoY |
|---|---|---|
| Interuniversity Microelectronics Centre (IMEC) | 0 | — |
| Taiwan Semiconductor Manufacturing Company Limited (TSMC) | 0 | — |
| Applied Materials, Inc. | 0 | — |
| QUALCOMM Incorporated | 0 | — |
| Intel Corporation | 0 | — |
| Huawei Technologies Co., Ltd. | 0 | — |
| Tokyo Electron Limited | 0 | — |
| Semiconductor Manufacturing International (Beijing) Corporation (SMIC Beijing) | 0 | — |
Where to take this analysis
The filing and citation pattern raises follow-up questions that are easier to answer with claim-level search than with aggregate counts alone.
Map the monolithic vs. sequential CFET split
The dataset mixes monolithic (single-tier, sequential low-temperature processing) and wafer-bonded sequential CFET approaches under one search string; separating them would show which route is actually being claimed more heavily.
Explore in Eureka →Track the process-vs-architecture citation gap
Because the top-cited record is a thermal-budget process claim rather than a device-geometry claim, a deeper claim-scope comparison could clarify whether new entrants should target process integration or structural geometry first.
Run a claim comparison in Eureka →Watch publication-lag-affected recent years
2025 and 2026 filings are undercounted in this snapshot; revisiting the trend in a future cut will reveal whether the 2023 peak was a one-off or the start of a new filing wave.
Set up monitoring in Eureka →Common questions about CFET patents
A Complementary FET stacks an n-type and a p-type field-effect transistor vertically within a single device footprint, rather than placing them side by side as in conventional planar or FinFET logic. This vertical stacking is what lets chipmakers keep shrinking logic density once lateral scaling runs out of room. Because the architecture touches gate stack design, source/drain contact formation, and sequential or monolithic 3D integration all at once, patent claims in this area cluster in gate-structure and general semiconductor-device IPC classes rather than a single dedicated one.
The tracked dataset contains 41 patent families filed between 2015 and mid-2026, which is a small pool compared to mainstream transistor technologies. Filing activity rose from zero in 2017 to a peak of 23 in 2023, but the years around and after that peak show no confirmed sustained acceleration once you account for the roughly 18-month lag between filing and publication. That combination — a real but short-lived peak, followed by a flatter trend — points to an early-stage field where the core architecture claims are already being staked out.
The assignee list is led by large foundries, integrated device manufacturers and semiconductor equipment suppliers rather than fabless design firms, reflecting how much of CFET's value sits in process integration rather than pure circuit design. Every top assignee in this dataset shows zero filings in the most recent tracked year, which is expected given publication lag rather than evidence that any of them have stepped back. Co-filing between separate corporate groups is rare, with only three co-assignee pairs identified across the whole dataset.
EP4569539A1, filed by QUALCOMM INCORPORATED and published 2025-06-18, covers monolithic three-dimensional CFET circuits and their manufacturing method — the single-tier, sequentially processed integration route rather than wafer-bonded sequential CFET. Anyone designing within that same monolithic route needs to check its specific process and structural claims closely before finalizing a fabrication flow. Teams pursuing the alternative sequential wafer-bonding approach, or working on source/drain contact formation and inner-spacer deposition specifically, sit further from this filing's claim scope.
Based on the IPC spread and citation pattern in this dataset, thinner-filed sub-areas include confined source/drain contact formation, carbon-doped sacrificial release layers used in monolithic stacking, and low-thermal-budget sequential integration methods. These sit adjacent to the most-cited records rather than duplicating them, meaning a well-drafted claim there would not simply be re-treading occupied ground. That said, thin filing density in a 41-family dataset can also mean a sub-area is genuinely early rather than permanently open, so any freedom-to-operate conclusion should be paired with a live claim-scope search before filing.
Research Complementary FET Transistor Architecture in depth with Eureka
Go past this page: query the whole complementary fet transistor architecture corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.