Complementary FET Wafer Bonding Patents: Who Leads, Gaps 2026
- A thin, flat filing record. 15 families total, peaking at 4 in 2019, with the 2022 midpoint back at zero — this is a technology with claims still being staked, not consolidated.
- No single assignee is currently active. Every tracked assignee, including Intel, shows zero filings in the latest year, some down 100% year-on-year — momentum has stalled across the board, not just for laggards.
- Filing is split across five receiving offices. US, EPO, WIPO, Germany and the UK each hold filings, meaning defensible positions require a multi-jurisdiction view rather than a single-market read.
Filing growth compares 2021 (1 records) with 2024 (1) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this patent set covers
Complementary FET (CFET) architectures stack an n-type and p-type transistor vertically to shrink cell footprint beyond what side-by-side finFET or gate-all-around layouts allow. Building that stack requires either monolithic sequential integration — growing the second device tier directly on the first — or wafer-to-wafer bonding and layer transfer, where two separately processed tiers are joined and thinned. This dataset isolates the second route: filings that combine CFET terminology with bonding, sequential-integration, hybrid-bonding, or layer-transfer language in the claims or description, under the semiconductor-device IPC classes that cover wafer processing and bonding.
At 15 published families, the corpus is small enough that individual filings matter more than aggregate trends. Publication lags filing by roughly 18 months, so any apparent drop in the most recent year understates real activity rather than confirming a slowdown.
Filing trend and technology composition
The two views below track when families were filed and how they are classified. Read the trend as directional rather than exact for 2024–2026, since publication delay hides recent filings that have not yet surfaced.
A peak in 2019, then a flat-to-declining line
Filings rose to 4 in 2019 and have not returned to that level since; the 2022 midpoint sits at zero. That shape is consistent with an early flurry of foundational claims followed by a pause, rather than steady, compounding investment.
Concentrated in general semiconductor-device classes
All 15 records sit under H01L, with 8 also tagged to the newer H10D general semiconductor-device class and 4 to H10P — a narrow classification footprint that reflects how young and unsettled the CFET-bonding intersection still is.
Shares are the percentage of the 15 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Complementary FET Wafer Bonding with Eureka
This page is one run against one query. Ask Eureka your own question about complementary fet wafer bonding and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited records and a representative filing
EP4791148A1 — Complementary field-effect transistor and method of manufacture
In some examples, a complementary field-effect transistor (CFET) comprises a first transistor formed on a first level, and a second transistor formed on a second level, wherein the second level is stacked on the first level, wherein a channel of the first transistor is offset from a channel of the second transistor while maintaining partial overlap between the channels.Filed by Huawei Technologies Co., Ltd.; the offset-channel-with-partial-overlap limitation is the specific geometry to check against before designing a stacked-channel layout.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20230377998A1 | Method of forming confined growth s/d contact with selective deposition of inner spacer for cfet | 19 |
| 2 | US20210202326A1 | Method for manufacturing a CFET device | 6 |
| 3 | WO2020242909A1 | Compact 3D stacked CFET architecture for complex logic cells | 3 |
| 4 | US11876020B2 | Method for manufacturing a CFET device | 1 |
Citation counts reward older filings simply because they have had more time to be cited; treat this table as a map of early influence, not of which claims matter most today.
Publication numbers are shown where the record carries one (4 of 4 rows); clicking a row searches Eureka by that number.
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Three patterns stand out once the dataset is this small: the technology's classification is narrow, its filing history is uneven, and its citation record is dominated by a single family.
A field still being staked, not settled
With only 15 families across more than a decade of coverage, no assignee has built a defensive thicket here. A well-drafted claim on an under-covered bonding step still has room to stand largely alone.
One family carries most of the influence
US20230377998A1, on confined-growth source/drain contact formation for CFET, is cited far more than any other record in the set. Anything touching selective-deposition inner-spacer or S/D contact confinement should be checked against it first.
No single dominant filing venue
The 15 families split across five receiving offices with the US only slightly ahead of Europe and PCT filings. A freedom-to-operate check confined to one jurisdiction will miss live filings elsewhere.
Activity has paused across every tracked assignee
Every assignee in the momentum data, including Intel at -100% YoY, shows zero filings in the latest year. That is either a genuine pause or a publication-lag artifact — either way, current searches will undercount what is actually in the pipeline.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to complementary fet wafer bonding, with the prior art for and against each one.
Who holds the ground, and where it is open
The assignee list is short and no one is currently filing at volume. That combination — low activity, unconsolidated ownership — is the clearest signal in this dataset.
A roster of large players, all currently quiet
Soitec, International Business Machines Corporation (IBM) (IBM), Tokyo Electron Limited (Tokyo Electron) and Intel Corporation (Intel) all appear in the ranking, and all show zero filings in the latest tracked year. This is a dormant-looking field held by companies with deep process-integration expertise elsewhere.
Corporate-affiliate filing, not cross-company alliance
The two identified co-assignee pairs — Tokyo Electron with its US holding entity, and IBM with IBM China — are internal corporate structures rather than joint ventures between competitors. There is no evidence here of collaborative R&D across independent firms.
Contact and spacer formation is the most-referenced ground
The highest-cited record in the set addresses confined source/drain contact growth with selective inner-spacer deposition for CFET. Later filers in that specific process step will need to design around or license around this claim.
| Assignee | Recent year | YoY |
|---|---|---|
| Soitec | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Tokyo Electron Limited | 0 | — |
| Intel Corporation | 0 | -100% |
| Tokyo Electron U.S. Holdings, Inc. | 0 | — |
| IBM (China) Co., Ltd. | 0 | — |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | -100% |
| Huawei Technologies Co., Ltd. | 0 | -100% |
Where to take this analysis
This landscape flags the shape of the field; deciding where to file or how to design around specific claims needs a closer read of individual documents.
Check freedom-to-operate on contact formation
Before drafting claims touching source/drain contact or inner-spacer steps for CFET, review the top-cited record's independent claims in detail rather than relying on the abstract.
Explore in EurekaMap the white space chips against your own roadmap
The under-claimed sub-areas listed above are starting points, not conclusions — run a targeted search against your specific bonding or layer-transfer method to confirm the gap holds.
Run a search in EurekaCommon questions about CFET wafer bonding patents
CFET wafer bonding refers to building a complementary FET stack — an n-type and p-type transistor placed vertically on top of each other — by separately processing two wafers or tiers and then joining them through bonding and layer transfer, rather than growing both devices sequentially on one substrate. This approach is one of two main routes to CFET integration, the other being monolithic sequential integration on a single wafer. Patent filings in this space combine CFET-specific device claims with bonding, hybrid-bonding, or layer-transfer process claims, typically under semiconductor-device IPC classes covering wafer processing.
This dataset identifies 15 published patent families matching CFET terminology combined with wafer-bonding or layer-transfer language, filed between 2015 and the mid-2026 data cut-off. That is a small corpus by semiconductor standards, reflecting how recently CFET has moved from research concept toward integration engineering. Filing peaked at 4 families in 2019 and has not returned to that level since, though publication lag of roughly 18 months means the most recent years are undercounted.
The named assignees in this dataset include Soitec, IBM (and its China entity), Tokyo Electron (and its US holding entity), and Intel, among others — companies with established process-integration or wafer-bonding expertise. None of them shows active filing in the latest tracked year, so the current ranking reflects historical positioning rather than an active filing race. The field remains unconsolidated: no assignee holds a dominant share of the 15 families.
Based on claim density relative to process importance, under-claimed areas include bonded-interface via alignment for stacked tiers, selective inner-spacer deposition outside the specific source/drain contact context already claimed by the top-cited record, thermal budget management across bonded tiers, and cross-tier interconnect formation after layer transfer. These are process steps essential to making CFET bonding manufacturable at scale, yet they show comparatively little dedicated claim coverage in this corpus. Confirming any of these as genuinely open requires a targeted search beyond this landscape's scope.
Every assignee tracked in the momentum data shows zero filings in the latest year, but this should not be read as the field going cold. Patent publication typically lags actual filing by around 18 months, so filings made in the last year or two of the coverage window have not yet appeared in the public record. The more reliable signal is the multi-year pattern — a 2019 peak followed by an uneven, generally flat trend — rather than the final year's apparent silence.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.