The dataset's assignee ranking is dominated by established electronics and materials firms with long filing histories in III-V and crystal-growth technology, including names such as Sumitomo Electric Industries, Sony, Toshiba, Fujitsu and Soitec, alongside research consortia like IMEC. None of the tracked assignees show filings in the most recent year, which points to a period of consolidation rather than active new claim-staking. Readers evaluating freedom-to-operate should look at each assignee's full family history rather than just recent activity, since older grants often carry the broadest and most-cited claims.

Filings peaked in 2017 at 29 records and had fallen to roughly 6 by the 2022 midpoint, with the most recent year showing no completed filings in this dataset. This flat-to-declining trend should be read with the caveat that publication typically lags filing by about 18 months, so the last one to two years are undercounted. Taken together, the pattern suggests the core process claims were staked out in the mid-2010s and the field has since moved toward incremental refinement rather than a new filing wave.

Molecular beam epitaxy (MBE) growth claims generally cover layer-by-layer deposition of III-V material across a substrate, while selective area growth claims specify deposition confined to defined openings, typically etched through an oxide or dummy layer, as seen in the representative IMEC record covering stacked III-V channel formation. The two are often combined in a single fabrication sequence, and dense IPC overlap between C30B (crystal growth) and H01L (semiconductor devices) reflects that combination. Distinguishing which mechanism a target patent actually claims is important, because broad MBE method claims are harder to design around than a narrow, geometry-specific selective-area-growth step.

The United States leads by a wide margin with 325 records in this dataset, followed by the European Patent Office at 102 and Japan at 64; the WIPO/PCT route accounts for 54 filings, with Australia and the United Kingdom each under 20. This concentration suggests the US and Europe carry the deepest prior art and the most contested claim space, while jurisdictions like the UK and Australia have comparatively thinner coverage and may offer more room for a regional filing strategy.

US20170178971A1, assigned to IMEC and filed in 2017, claims a specific method of forming a III-V channel layer on silicon by depositing and later replacing a sacrificial dummy layer through etched via-holes using selective area growth. It blocks that particular dummy-layer-replacement sequence but does not cover III-V-on-silicon integration generally; direct epitaxial growth or wafer-bonding approaches, such as the silicon/III-V bonding method that is among the most-cited records in this space, sit outside its scope. Anyone building a CMOS device with a stacked III-V channel should check their process flow against this specific mechanism rather than assuming broader coverage.