The assignee ranking behind this dataset covers 100 companies, with the leading filer holding 2,284 records, well ahead of fifth place at 547 and tenth place at 283. The top five combined account for 34.2% of all 15,398 records in scope, so concentration is heavy at the very top even though the ranking runs into a long tail of smaller filers. Foundries and large integrated device manufacturers dominate the top of that list, with university and research filers appearing further down.

Filing volume peaked at 905 in 2022 and, on the last fully comparable years, fell from 709 filings in 2021 to 547 in 2024 — a 23% decline. That is a genuine pull-back rather than a data artefact, since both years are old enough to be fully published. Figures for 2025 and 2026 look lower still, but that reflects the roughly 18-month lag between filing and publication, not a further collapse in activity.

H01L (semiconductor devices) is the dominant classification, appearing on 83.7% of the 15,398 records in scope. H10D, H10P and H10W split out more specific device, packaging and wafer-level claims, while H01S covers laser and stimulated-emission devices at 5.7% and G02B covers optical elements at 3.4%. Because a single record can carry several IPC codes, these shares add up to well over 100% and should not be read as a partition of the field.

The clearest under-claimed territory sits adjacent to the dominant H01L block rather than inside it: wafer-level packaging for wide-bandgap devices, laser-adjacent integration under H01S, and memory-device fabrication on compound substrates under H10B all show comparatively thin filing density relative to their technical relevance. A first claim in these areas would need to combine a specific fabrication step with a compound semiconductor context to fall inside the same scope this dataset tracks. Searching only the core H01L classification will miss most of this space.

US4981809A, assigned to Sumitomo Electric Industries, claims a compound semiconductor device with source and drain regions either side of a substrate groove, a shallower separating region, a deeper region between the source and drain carrying a Schottky gate contact, and the specific mask-pattern method used to produce that groove structure. It blocks that particular groove-and-Schottky geometry and the disclosed patterning method, not compound semiconductor transistors generally. Anyone designing a similar recessed-gate structure should check whether their approach reproduces this specific groove-and-region arrangement or diverges from it, for example by using a different gate contact type or a non-grooved substrate.