The classical challenge of sub-wavelength lithography is captured by the resolution formula CD = k1 × λ/NA, where the process factor k1 must be pushed below 0.5 for advanced logic nodes. Computational lithography addresses this by formulating source and mask design as a coupled optimization problem governed by multi-variable cost functions. Early sequential approaches optimized the source and mask independently — an approach now recognized as suboptimal. As documented in the Fast Freeform Source and Mask Co-optimization patent (Ye/ASML, 2010), existing algorithms could not perform simultaneous optimization of both source and mask; instead they discretized illumination into independent source points and mask into diffraction orders in the spatial frequency domain, then separately formulated a cost function. The invention overcame this limitation by enabling direct computation of the gradient of the cost function, allowing simultaneous and freeform co-optimization that significantly accelerated convergence.

IBM's contributions center on iterative joint optimization architectures — a structured three-stage method comprising standalone mask optimization, standalone light source optimization, and then joint light source-mask optimization, all governed by a unified set of parameters including variable representation, objectives, and problem constraints. This architecture provides a systematic framework for ensuring convergence toward a globally consistent solution rather than a locally optimal one for either the source or the mask independently. The PatSnap Analytics platform enables researchers to map these patent families and track citation lineage across IBM, ASML, and academic filers.

Parametric representations of source and mask offer an important bridge between mathematical optimization and physically realizable hardware. The Beijing Institute of Technology's 2014 parametric SMNO method simultaneously optimizes source shape, mask pattern, and numerical aperture using an analytic cost function based on an integrative vector imaging model — addressing the fundamental tradeoff that higher NA yields finer resolution at the cost of reduced depth of focus (DOF). According to WIPO patent data, this area of parametric co-optimization has seen sustained filing activity across multiple jurisdictions.

Mentor Graphics Corporation independently developed Lagrange-based source optimization coupled with diffraction-order-driven continuous tone mask generation, applying homotopy methods to refine both source and mask against band-limited target frequencies — providing a physics-grounded pathway from optimization to manufacturable mask shapes. These developments collectively represent the foundation upon which all modern SMO frameworks are built.

ASML Netherlands B.V. is by far the dominant patent filer in this dataset, with contributions spanning every major subdomain: freeform SMO, discrete pupil optimization, diffraction-guided pupil construction, SMLO, stochastic-aware SMO, across-slit variation compensation, source spectra optimization for depth of focus, and diffraction pattern-based SMO. The breadth and continuity of ASML's portfolio — from 2010 through projected 2026 filings — reflects its role as the primary supplier of both the lithographic hardware (scanners with programmable pupil systems) and the computational lithography software infrastructure. Key technical trajectories include the shift from parametric to freeform optimization, the incorporation of 3D resist models, and the introduction of diffraction physics as a pupil initialization strategy.

International Business Machines Corporation (IBM) contributes a distinct intellectual thread focused on joint source, mask, and target optimization with process variation integration, fractional resist shot noise (FRSN)-based line width roughness control, and contour-based circuit quality assessment. IBM's method explicitly couples SMO to physical noise models through the FRSN parameter, predicting edge roughness as a function of optical intensity distribution — a methodology directly relevant to EUV metrology standards where stochastic noise is a primary yield limiter.

IMEC contributes foundational work on illumination source shape definition, introducing a two-stage optimization strategy: a first pass with non-rectangular sub-resolution assist features (SRAFs) to maximize image quality, followed by a second pass constrained to rectangular SRAFs to limit mask complexity. This hierarchical approach represents a practical engineering compromise between lithographic performance and mask manufacturability. The PatSnap Life Sciences platform similarly applies multi-stage optimization logic to biological research workflows.

Mentor Graphics Corporation (now Siemens EDA) developed pattern-selection-based full-chip SMO and layout content analysis tools. Pattern matching across the full chip layout identifies and consolidates similar patterns into groups, allowing SMO to run on a representative subset while maintaining full-chip coverage — a critical scalability innovation for production SMO flows. Samsung Electronics has entered the active patent landscape with source system optimization using aerial image NILS as the objective function (2025), signaling growing in-house computational lithography capability among logic chip manufacturers. According to the IEEE, NILS is a primary metric governing resist exposure and line edge roughness in advanced node patterning.

Academic contributors — including the Beijing Institute of Technology, Huazhong University of Science and Technology, and the University of Chinese Academy of Sciences — have advanced parametric multi-parameter co-optimization methods, inverse lithography with mask filtering for manufacturability, and hybrid genetic algorithm approaches. The normalized conjugate gradient algorithm introduced by the Beijing Institute of Technology improves convergence efficiency across parameters of different scales. Explore the full academic patent landscape using PatSnap Analytics to track citation networks and filing velocity.