Compute-in-Memory Patents: Leaders, Trends & White Space 2026
- Filing already peaked. 2018 recorded the most publications in this corpus (6), with the 2022 midpoint down to 2 — a flat-to-declining trend rather than a growing one.
- One family line dominates citations. The multi-VDD analog-multiplier compute-in-memory family (US20190042199A1 and its continuations) draws 233 citations, far ahead of any other record in the set.
- Momentum has shifted to new individual filers. The only assignees active in the latest year are two individual co-filers, not the incumbents who built the early citation base.
What this patent landscape covers
This dataset tracks patent families combining compute-in-memory, processing-in-memory and in-memory computing terminology with claim language around analog matrix multiplication, device variation, ADC overhead, energy per operation and mapping algorithms, filtered to IPC classes covering static and digital memory, AI-model computing, and general digital data processing. It is a narrow, claim-specific slice of the broader in-memory computing field rather than a survey of the whole architecture space.
Fifteen published records span 2015 through the 2026 cut-off, with filings concentrated in a handful of priority years and a citation profile dominated by a small number of foundational disclosures. Because publication typically lags filing by around 18 months, the most recent year on the trend line understates actual filing activity.
Filing trend and technology composition
Fifteen families, four receiving offices, and a technology mix that skews heavily toward AI-model computing and static/digital memory classifications.
A peak in 2018, then a decline
Filings rose to 6 in 2018, the high point of the corpus, then fell back toward the 2022 midpoint of 2. The 2026 figure of 1 is partial and will rise somewhat as later filings publish, but the shape of the curve — an early peak followed by a long, thin tail — is unlikely to reverse.
Concentrated in two IPC subclasses
G06N (AI-model computing) and G11C (static and digital memories) account for the large majority of records, 13 and 12 respectively out of 15. G06F, H01L, B82Y and G06G appear only a handful of times each, indicating that claim activity clusters tightly around the memory-array and neural-computation intersection rather than spreading across adjacent semiconductor or analogue-computing classes.
Shares are the percentage of the 15 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Compute-in-Memory Architectures with Eureka
This page is one run against one query. Ask Eureka your own question about compute-in-memory architectures and every answer comes back with the patent numbers behind it.
Try EurekaThe records other filings build on
Adaptive quantization method for analog in-memory computing systems
Filed by The Hong Kong University of Science and Technology, this application describes adaptively quantizing parameters for deployment on magnetic-memory-based in-memory computing systems, using a conductance-shift sensing process and a lookup table to round parameter values to the nearest recorded conductance shift.Published 2025-04-10 as US20250117661A1.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20190042199A1 | Compute in memory circuits with multi-VDD arrays and/or analog multipliers | 233 |
| 2 | US20190080231A1 | Analog switched-capacitor neural network | 72 |
| 3 | US11061646B2 | Compute in memory circuits with multi-Vdd arrays and/or analog multipliers | 18 |
| 4 | WO2020068307A1 | Compute in memory circuits with multi-VDD arrays and/or analog multipliers | 4 |
| 5 | WO2019051354A1 | Analog switched-capacitor neural network | 4 |
| 6 | CN117574767A | 存内计算架构软硬件系统仿真方法和仿真器 | 3 |
| 7 | US11263522B2 | Analog switched-capacitor neural network | 2 |
| 8 | US20250117661A1 | Adaptive quantization method for analog in-memory computing systems | 1 |
| 9 | US12061977B2 | Analog switched-capacitor neural network | 1 |
Citation counts inside a searched corpus favour older, foundational filings — treat them as a signal of influence on subsequent claim drafting, not as a measure of current commercial relevance.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Publication numbers are shown where the record carries one (9 of 9 rows); clicking a row searches Eureka by that number.
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Three things stand out once the raw counts are read against filing dates and citation weight rather than taken at face value.
The core claim space was staked out early
Most of the citation weight in this corpus traces back to filings from the 2018 peak. Later entrants are filing around the edges of that early claim territory rather than displacing it, which is consistent with a technology whose foundational circuit-level claims were settled before the field's more recent AI-driven attention arrived.
One family line anchors the prior art
The multi-VDD, analog-multiplier compute-in-memory family — spanning a US application, a granted US patent, and a WIPO counterpart — accounts for the dominant share of citations in the set. Anyone drafting claims on analog multiplier arrays inside a compute-in-memory cell should expect this family to surface in any freedom-to-operate search.
Named incumbents have gone quiet
Assignees with the deepest historical presence in this set — including the semiconductor and university players behind the highest-cited records — show no filings in the latest tracked year. The only latest-year activity comes from two individual co-filers, a pattern more typical of a niche cooling off than one still building institutional patent estates.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to compute-in-memory architectures, with the prior art for and against each one.
Who holds the claims, and where the gate sits
Assignee activity in this corpus is thin and uneven: a small number of institutional filers built the early citation base, two co-assignee pairs show any collaboration at all, and the most recent filings come from individuals rather than firms.
Collaboration is the exception, not the rule
Only two co-assignee pairings appear in the full set. The strongest links a semiconductor firm with a university research office, suggesting a sponsored-research arrangement rather than a broad industry consortium around compute-in-memory circuit design.
New entrants are individuals, not incumbents
The two assignees with any activity in the latest year are named individuals rather than corporations or universities. That is a marked shift from the institutional filers who hold the high-citation records, and it suggests the next wave of filing in this niche may come from smaller, independent inventors.
Filing is US-centred with an India signal
United States filings lead the set at 8, with India and WIPO PCT filings each at 3 and a single Chinese filing. The India count is notable for a corpus this size and points to at least one active filer or institution pursuing protection there alongside the US route.
| Assignee | Recent year | YoY |
|---|---|---|
| IRUKUMALLI PRIYANKA | 1 | — |
| BAPATLA SURENDRA BABU | 1 | — |
| Analog Devices, Inc. | 0 | — |
| Intel Corporation | 0 | — |
| The Trustees of Princeton University | 0 | — |
| Indian Institute of Technology Indore | 0 | — |
| The Hong Kong University of Science and Technology | 0 | — |
| Xi'an Jiaotong University | 0 | — |
Where to take this analysis
The filing pattern here raises questions a static table cannot answer on its own — Eureka's analysis tools are built for exactly this next step.
Check freedom-to-operate against the top-cited family
Before drafting claims on analog multiplier arrays inside a memory cell, run a full claim-scope comparison against the multi-VDD family that anchors this corpus's citations.
Run a claim comparison in EurekaTrack the individual filers now active in this niche
The assignees with the only latest-year activity are individuals, not the incumbents. Monitoring their filing history may surface where the next wave of claims lands.
Set up assignee tracking in EurekaMap the under-claimed branches before committing R&D
ADC overhead reduction and device-variation compensation show up in the search terms but not in dense claim clusters — worth a deeper white-space pass before investing.
Explore white space in EurekaCommon questions about compute-in-memory patents
In this corpus, the most-cited records all trace to a single family built around multi-VDD arrays and analog multipliers, published first as a US application and later as a granted US patent and a WIPO counterpart, with 233 citations on the earliest filing. That level of citation concentration means most later compute-in-memory circuit filings in this space reference back to that one family. It is a useful starting point for any freedom-to-operate search on analog-multiplier memory arrays, though citation counts favour older filings and should not be read as a measure of current market strength.
Not in this dataset. Filings peaked in 2018 at six records and had fallen to two by the 2022 midpoint, which is a flat-to-declining pattern rather than sustained growth. The 2026 count of one is partial because publication lags filing by roughly 18 months, so some additional recent filings will still surface. Even allowing for that lag, the overall shape points to a technology whose core claim territory was staked out several years ago rather than one still expanding rapidly.
IPC classification shows heavy overlap with G06N, covering AI-model computing, and G11C, covering static and digital memories — 13 and 12 of the 15 records respectively. Smaller overlaps appear with general digital data processing, semiconductor devices, nanotechnology and analogue computers. This tells filers that compute-in-memory claims in this corpus sit squarely at the intersection of memory-array hardware and neural-network computation, with limited spread into adjacent semiconductor fabrication or analogue circuit classes.
The search terms behind this corpus include ADC overhead, device variation, energy per operation and mapping algorithms, but claim density around several of these — particularly ADC overhead reduction and device-variation compensation — is thin relative to the core array-and-multiplier claims. That gap suggests room to file narrowly scoped claims on calibration, quantization or mapping techniques without running into the dense prior art that covers the underlying array architecture itself. A design-around or white-space search focused specifically on those terms is a reasonable next step before committing engineering resources.
The United States leads with 8 filings in this corpus, followed by India and WIPO PCT applications at 3 each and a single filing in China. The India figure is worth noting for a set this size, since it points to at least one active filer pursuing protection there alongside the more typical US and PCT routes. Applicants weighing where to seek protection should treat the US as the primary jurisdiction reflected in this data, with India as a secondary market showing genuine activity rather than incidental coverage.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.