Contact & MOL Resistance Patents: Who Leads, Filing Trends 2026
- 33.3% of all 4,144 records sit with just five assignees, and the top ten combined reach 45.6% — this is a field with a concentrated head and a long tail behind it.
- Filing peaked in 2017 at 240 and the 2021→2024 complete-year window shows a 24% decline, though 2025-2026 figures are still filling in under publication lag.
- H10D, H10P and H10W together cover a meaningful share of records outside the core H01L class, pointing to where MOL integration claims are being staked beyond the traditional semiconductor-device subclass.
Filing growth compares 2021 (210 records) with 2024 (160) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 4,144 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Contact and middle-of-line (MOL) resistance is the part of logic device manufacturing concerned with getting current through the silicide-to-metal interface and the contact/via stack without losing performance to parasitic resistance. This dataset spans 4,144 patent records published between 2015 and mid-2026, drawn from filings that combine language around contact resistance, silicide formation and middle-of-line integration with specific engineering levers — schottky barrier height, wrap-around contacts, liner scaling, metal resistivity and via resistance.
The records are dominated by core semiconductor-device classification but extend into memory manufacture, coating and deposition, and digital processing classes, reflecting how contact engineering touches process integration as much as device architecture.
Filing trend and technology composition
Two views of the same 4,144-record corpus: how filing activity has moved year over year, and which IPC subclasses carry the claims.
Filing trend, 2017-2026
Filings peaked at 240 in 2017. Across the last complete-year window, 2021 (210) to 2024 (160), volume fell 24%. Years from 2025 onward are still under-counted because publication typically lags filing by about 18 months, so the apparent drop at the very end of the chart should not be read as the field slowing further.
IPC subclass distribution
H01L covers 82.6% of the 4,144 records, consistent with contact and MOL resistance being classified primarily as core semiconductor-device technology. H10D, H10P and H10W each cover a double-digit or near-double-digit share, and smaller shares in H10B, G06F and C23C show the technology's reach into memory manufacture, digital processing and surface coating. Because records can carry multiple classes, these shares sum to more than 100% of the record total.
Shares are the percentage of the 4,144 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Contact and Middle of Line Resistance with Eureka
This page is one run against one query. Ask Eureka your own question about contact and middle of line resistance and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited records and a representative filing
US20120018815A1 — Semiconductor device with reduced contact resistance and method of manufacturing thereof
A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.Filed by Alsephina Innovations Inc., dated 2012-01-26.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US9105490B2 | Contact structure of semiconductor device | 1,640 |
| 2 | US8823065B2 | Contact structure of semiconductor device | 1,342 |
| 3 | US5573692A | Platinum heater for electrical smoking article having ohmic contact | 744 |
| 4 | US20020068458A1 | Method for integrated in-situ cleaning and susequent atomic layer deposition within a single processing chamb… | 669 |
| 5 | US6017818A | Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density | 649 |
| 6 | US20080143906A1 | Nanowire-based transparent conductors and applications thereof | 531 |
| 7 | US20020001976A1 | Chamber for constructing a film on a semiconductor wafer | 519 |
| 8 | US20100163937A1 | Methods of forming nickel sulfide film on a semiconductor device | 512 |
| 9 | US6187672B1 | Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing | 512 |
| 10 | US20160372365A1 | Method for forming metal chalcogenide thin films on a semiconductor device | 508 |
Citation counts favour older filings that have had more time to accumulate references within this corpus; treat them as a signal of influence on the field, not a ranking of current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three read-outs from the concentration, trend and citation data that matter for anyone deciding where to file or challenge.
The head of the field is narrow
Five assignees hold a third of all records in scope, and the next five push combined share to 45.6%. For a field spanning a decade of filings, that is a tight cluster — freedom-to-operate work in core contact and MOL claims should expect dense prior art from a small set of holders.
Volume has eased from its 2017 peak
The peak year, 2017 at 240 filings, has not been matched since. The most recent complete comparison, 2021 to 2024, shows a 24% decline. Years after 2024 are still filling in due to publication lag and should not be read as confirming a further drop.
Two contact-structure patents anchor the citation graph
The two most-cited records in the corpus are both titled around contact structure of semiconductor devices, cited 1,640 and 1,342 times respectively. Older process-chemistry patents on barrier films and in-situ cleaning also carry substantial citation weight, showing the field's roots in materials and integration process work.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to contact and middle of line resistance, with the prior art for and against each one.
Who is filing, and where momentum sits now
The ranked leaders come from a 100-company ranking drawn from the full 4,144-record set. Recent-year momentum figures show nearly every tracked leader pulling back from prior-year levels, consistent with the publication-lag effect rather than a genuine retreat from the technology.
One filer sits well ahead of the field
The top-ranked assignee holds 426 records, more than double the fifth-place holder's 166. That gap at the very top is unusual and suggests a filer that has treated contact and MOL resistance as a core patenting program rather than an incidental output of device work.
A steep drop-off after the top ten
Tenth place holds 63 records, well below the leader's 426 and below fifth place's 166. The curve from first to tenth is steep, then the ranking runs on to 100 companies with much thinner individual counts — a long tail of firms with narrower, more targeted filing programs.
Nearly every tracked leader shows a pullback
Recent-year momentum for the tracked leaders is uniformly negative, from -67% to -100% year over year. Given that publication lags filing by roughly 18 months, this pattern most likely reflects incomplete recent-year data rather than leaders abandoning the space.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 2 | -93% |
| Monolithic 3D Inc. | 1 | -86% |
| Intel Corp. | 1 | -67% |
| Samsung Electronics Co., Ltd. | 1 | -75% |
| International Business Machines Corporation (IBM) | 0 | -100% |
| Toshiba Corporation | 0 | -100% |
| Applied Materials, Inc. | 0 | -100% |
| Acorn Technologies, Inc. | 0 | — |
Where to take this
The concentration and trend data point to specific next steps depending on whether you are filing, licensing or challenging.
Map freedom-to-operate against the top holders
With a third of records held by five assignees, a claims map against those portfolios specifically — rather than the field broadly — will surface the real blocking risk for new contact or MOL integration work.
Explore assignee portfolios in EurekaWatch the under-claimed branches
Wrap-around contact geometry and interface engineering at the silicide-metal boundary carry fewer records relative to their engineering importance, which is where a well-drafted first claim has room to stand.
Run a white-space search in EurekaCommon questions on contact and MOL resistance patents
The leading assignee in this dataset holds 426 of the 4,144 records in scope, more than double the fifth-ranked holder's 166. The top five assignees combined account for 33.3% of all records, and the top ten reach 45.6%. That leaves a long tail across the remaining ranked companies, each with narrower filing programs focused on specific process steps or device architectures.
Filing peaked in 2017 at 240 records and has not returned to that level since. Comparing the most recent complete years, 2021 (210 filings) to 2024 (160 filings), volume fell 24%. Figures for 2025 and 2026 appear lower still, but that reflects publication lag of roughly 18 months rather than an actual collapse in activity, so treat the very end of the trend line as incomplete.
The bulk of records, 82.6% of the 4,144 in scope, classify under H01L for core semiconductor devices, with meaningful additional coverage in H10D, H10P and H10W device-architecture subclasses. Smaller but notable shares extend into memory device manufacture (H10B), digital data processing (G06F) and coating and surface deposition (C23C), reflecting how contact engineering intersects with adjacent process and system domains.
US20120018815A1, assigned to Alsephina Innovations Inc. and dated 2012-01-26, covers a method and device for reducing contact resistance in a field effect transistor by implanting an impurity in the source/drain regions after silicide formation, then performing a spike anneal that lowers the schottky barrier height at the silicide-junction interface. The claimed effect is a thinner, lower-resistance region at the silicide-semiconductor interface. Anyone working on post-silicide implant-and-anneal sequences for contact resistance reduction should review this filing's specific claim language before designing a similar process flow.
Wrap-around contact geometries, liner scaling at advanced nodes, and interface engineering at the silicide-metal boundary all show fewer records relative to their engineering significance in current node scaling. Via resistance in scaled interconnect stacks and low-resistivity metal fill alternatives are similarly under-represented next to the dense core contact-structure claims. These are reasonable areas to search more deeply before assuming the space is fully claimed, since concentration in this dataset sits heavily around core contact-structure and silicide-formation claims rather than these adjacent branches.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.