Cryogenic Readout IC Technology Landscape 2026
Cryogenic Readout IC Technology Landscape 2026
Cryogenic ROICs are accelerating across quantum computing, particle physics, and CMB observatories. This dataset spans 2006–2025 patent and literature signals from CERN, SLAC, ShanghaiTech, and beyond.
Six Sub-Domains Driving Cryogenic ROIC Innovation
Cryogenic readout integrated circuits are mixed-signal ASICs designed to operate at temperatures from 77 K down to sub-Kelvin regimes. The field spans at least six sub-domains: charge-sensitive preamplifiers, cryogenic SRAM and gain-cell eDRAM, ADC architectures, SQUID-coupled multiplexed readout for TES arrays, FDSOI and FinFET CMOS characterization, and cryogenic compute-in-memory accelerators.
The common technical demand across all sub-domains is that circuits retain functional margins, acceptable noise floors, and manageable power dissipation as temperatures drop from 77 K to 4.2 K and below — conditions that fundamentally alter CMOS threshold voltage, carrier mobility, subthreshold slope, and interface trap density.
Foundational activity in this dataset dates to a 2006 paper on CMS pixel detector readout and a 2011 CERN paper formalizing design guidelines for CMOS operation in liquid argon at approximately 89 K. By 2017, cryogenic monolithic CMOS preamplifiers for HPGe dark matter detectors had achieved ENC of 10.3 electrons at sub-pF input capacitances, signaling analog noise maturity at physics-competitive levels.
The most recent filings in this dataset (2024–2025) are dominated by ShanghaiTech University and the Institute of Modern Physics, Chinese Academy of Sciences — indicating a sharp rise in Chinese institutional IP activity. In retrieved records, US jurisdiction accounts for 6 of 10 patent records, followed by CN with 3 and WO with 1, with the three most prolific active assignees all being Chinese academic institutions filing in US jurisdiction.
Filing Activity by Jurisdiction and Technology Cluster
Among the patent records in this dataset, US jurisdiction dominates with 6 of 10 records, followed by CN with 3 and WO with 1. Technology clusters range from analog front-end ASICs and multiplexed SQUID readout to cryogenic gain-cell eDRAM and compute-in-memory accelerators.
Patent Records by Jurisdiction — Cryogenic ROIC (Dataset Snapshot)
In this dataset, US jurisdiction accounts for the largest share of retrieved cryogenic ROIC patent records (6 of 10), followed by CN (3) and WO (1).
↗ Click bars to explorePatent Activity by Technology Cluster — Cryogenic ROIC (Dataset Snapshot)
In this dataset, cryogenic gain-cell eDRAM and CIM accelerators represent the most recently active patent cluster (4 records, 2024–2025), while analog front-end CSA ASICs and module-level thermal management each account for 2 records dating from 2014–2020.
↗ Click bars to exploreCryogenic ROIC Deployment Across Physics, Space, and Quantum Systems
Cryogenic ROICs in this dataset are deployed across four primary application domains: particle physics and dark matter detection inside liquid argon and germanium cryostats, sub-Kelvin X-ray and CMB observatories, infrared focal plane arrays, and emerging cryogenic compute-in-memory systems co-located with quantum processors.
ATLAS HL-LHC & LAr-TPC
The ATLAS liquid argon calorimeter readout for the HL-LHC operates 182,500 channels at 40 MHz with 16-bit dynamic range, using 130 nm preamplifiers and 65 nm SAR ADCs. CERN’s 2011 cold-electronics-first architecture for giant LAr-TPCs established design guidelines for CMOS operation at approximately 89 K. The CDEX-10 design uses 14-bit 100 MSPS FADC chains with ZYNQ SoC readout for a 10 kg HPGe dark matter array at CJPL.
Particle PhysicsAthena X-IFU at 50 mK
The Athena X-IFU 50 mK test bench demonstrated readout of 2,000+ TES microcalorimeter pixels achieving 2.5 eV FWHM energy resolution, with cold-chain development across NASA, NIST, VTT, and SRON. SRON/VTT’s frequency-domain multiplexing readout simultaneously read 37 TES pixels at 2.23 eV energy resolution at 6 keV, developed for Athena X-IFU. SLAC’s SMuRF microwave SQUID platform targets 10,000–100,000 sub-Kelvin sensors per CMB camera using high-Q superconducting resonators.
X-ray & CMB ObservatoriesBrown University Infrared ROIC
Brown University’s 2025 WO patent pairs a custom CMOS ROIC with an HgCdTe photodiode array optimized for 3–10 μm infrared, achieving burst-mode thermal imaging at up to 5 million frames per second. A separate 2015 study demonstrated a 384×288 ROIC at 25 μm pixel pitch for MWIR and LWIR HgCdTe focal plane arrays. A 2018 study performed single-event effects radiation hardness testing of infrared sensor ROICs down to 50 K under heavy-ion irradiation for space mission qualification.
Infrared Focal Plane ArraysShanghaiTech Cryo CIM System
ShanghaiTech University’s 2024 CSDB-eDRAM patent achieves 16.67 s data retention time at 4.2 K — claimed as 2.6× the prior state-of-the-art — with 0.11 pW/Kb refresh power and 710 ps access time at 1.41 GHz. A companion 2024 cryogenic-in-memory-computing (CIMC) accelerator patent targets co-integration with quantum computing systems at 4.2 K. The 2022 CryoCiM publication demonstrated QAHE-based nonvolatile memory for CIM addressing the von-Neumann memory wall at cryogenic temperatures.
Cryogenic & Quantum ComputingLeading Patent Assignees in Cryogenic ROIC — Dataset Snapshot
In retrieved records, ShanghaiTech University is the most prolific single assignee with 4 active or pending US patents filed in 2024–2025, all targeting cryogenic gain-cell eDRAM and CIM accelerators. The Regents of the University of California hold 2 active US patents in this dataset covering module-level cryogenic thermal management.
Top Assignees by Patent Filing Count — Cryogenic ROIC (Dataset Snapshot)
↗ Click bars to exploreShanghaiTech University
ShanghaiTech University holds 4 active or pending US patents in this dataset, all filed between 2024 and 2025. Key filings cover a 16 Kb CSDB-eDRAM achieving 16.67 s retention at 4.2 K, a CQS-eDRAM with 4T transmission gate topology, and a cryogenic-in-memory-computing (CIMC) accelerator for quantum co-integration. All four patents are filed in US jurisdiction, with three currently active and one pending.
China — CN (filing in US)Regents of the University of California
The Regents of the University of California hold 2 active US patents in this dataset, filed in 2016 and 2019. Both patents cover the Active Cryogenic Electronic Envelope — a module-level thermal management approach enabling conventional electronics to remain warm inside a cryostat operating at 4 K. Both patents are currently active.
United StatesFive Emerging Directions in Cryogenic ROIC (2024–2025)
The five most recent filings in this dataset (all 2024–2025) point to three converging directions: cryogenic compute-in-memory at 4.2 K for quantum co-integration, quasi-static gain-cell eDRAM architectures, and burst-mode infrared ROICs at extreme frame rates.
Cryogenic Compute-in-Memory at 4.2 K
ShanghaiTech University’s 2024 CIMC accelerator patent signals a new application axis: cryogenic accelerator chips for AI/ML inference co-located with quantum processors. This goes beyond the traditional physics-detector motivation and targets the emerging quantum computing infrastructure market. The companion CQS-eDRAM patent (2025, pending) introduces a 4T transmission gate topology providing quasi-static operation at 4.2 K, an architectural innovation absent from prior literature on cryogenic SRAM.
Burst-Mode Thermal Imaging at 5 Mfps
Brown University’s WO 2025 patent claims up to 5 million frames per second for a CMOS ROIC paired with an HgCdTe photodiode array optimized for 3–10 μm infrared — orders of magnitude beyond prior-generation infrared ROICs. This pushes cryogenic ROIC bandwidth into high-speed scientific and defense imaging. A 2018 study had already demonstrated SEE qualification of infrared ROICs down to 50 K under heavy-ion irradiation, establishing a prior radiation-hardness baseline for space applications.
Cryogenic Gain-Cell eDRAM vs. 6T-SRAM for Embedded Memory at 4.2 K
Click any row to explore further.
| Dimension | Gain-Cell eDRAM (4.2 K) | 6T-SRAM (77 K) |
|---|---|---|
| Data Retention Time | 16.67 s (CSDB-eDRAM, 2.6× state-of-the-art claimed) | 900× improvement vs room temp (GC-eDRAM literature); 6T-SRAM retention not separately quantified at 77 K in this dataset |
| Refresh Power | 0.11 pW/Kb (CSDB-eDRAM, ShanghaiTech 2024) | N/A — 6T-SRAM has no refresh requirement but higher static leakage at 77 K |
| Access Time | 710 ps at 1.41 GHz (CSDB-eDRAM) | N/A — not quantified separately in dataset for 6T-SRAM at cryo |
| Write SNM at Low Temperature | Not quantified in this dataset for GC-eDRAM | −16% write static noise margin at 77 K vs room temperature (literature, 2021) |
| Read Margin (STT-MRAM reference) | N/A | STT-MRAM shows 36–48% improved read margin at cryogenic temps (2021 literature) |
| CIM Integration | Native — CQS-eDRAM patent explicitly targets CIM at 4.2 K; CIMC accelerator co-designed | Not demonstrated for CIM in this dataset |
| Topology | 4T transmission gate gain-cell (CQS-eDRAM, 2025 pending) | 6T standard cell (conventional) |
| Key Assignee (this dataset) | ShanghaiTech University (US patents, 2024–2025) | No dedicated patent assignee identified in this dataset |
Cryogenic Readout IC — Frequently Asked Questions
Based on the retrieved records, cryogenic ROICs are designed to operate reliably across temperatures ranging from 77 K down to sub-Kelvin regimes, with specific implementations documented at 89 K (liquid argon), 4.2 K (liquid helium), 1 K (HEMT front-end), 55 mK (Athena X-IFU TES arrays), and 50 K (infrared sensor SEE testing).
ShanghaiTech University holds 4 active or pending US patents in this dataset, all filed between 2024 and 2025, making it the most prolific single patent assignee in the retrieved records. The filings target cryogenic gain-cell eDRAM and compute-in-memory (CIM) accelerators for 4.2 K operation. This concentration signals a deliberate institutional IP strategy targeting US market protection in cryogenic memory and computing.
According to ShanghaiTech University’s 2024 US patent, the 16 Kb CSDB-eDRAM at 4.2 K achieves 16.67 s data retention time (claimed as 2.6× the state-of-the-art), 0.11 pW/Kb refresh power, and 710 ps access time at 1.41 GHz.
Based on literature in this dataset, 28 nm FDSOI (characterized to 4.2 K, 2019), 22 nm FDSOI (characterized to 5.5 K with extrapolated fT of 495 GHz, 2021), 180 nm CMOS (characterized to 100 mK, 2020), 350 nm and 180 nm CMOS (used for HPGe dark matter detector ASICs at cryogenic temperatures, 2017), and 130 nm and 65 nm (used for ATLAS HL-LHC readout, 2020) have all been documented.
Frequency-domain multiplexing (FDM) and microwave SQUID multiplexing allow large numbers of sub-Kelvin sensors to be read out with minimal thermal loading. The SLAC SMuRF platform targets 10,000–100,000 sub-Kelvin sensors per camera; the POLARBEAR-2 system achieves a multiplexing factor of 40 for 7,588 TES bolometers; and SRON/VTT’s FDM demonstrated simultaneous readout of 37 TES pixels at 2.23 eV energy resolution at 6 keV for the Athena X-IFU.
According to the strategic analysis in this dataset, the absence of commercially qualified cryogenic compact models (PDKs) for sub-28 nm nodes is identified as the critical bottleneck. Without accurate compact models at cryogenic temperatures, ASIC designers cannot converge circuits for operation below 10 K, constraining design to empirical approaches. Foundry partnerships with TSMC, GlobalFoundries, and STMicroelectronics FDSOI are flagged as key areas to monitor.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.