CXL Memory Expansion and Pooling Patents: Who Leads 2026
- 260 families, one dominant filer with a sharp pullback. the leading recent-year assignee's filings fell 75% year over year, while most other active filers sit flat at zero or one filing — concentration without sustained momentum.
- Filing peaked in 2024 at 62, not in the most recent year. the climb from a 2022 midpoint of 43 to 62 in 2024 suggests the wave of foundational filing has already crested, ahead of any slowdown from publication lag.
- G06F dominates every record; H04L and H04W trail far behind. claims cluster on core data-processing architecture (all 260 records), with networking and wireless integration only lightly claimed — a gap for fabric-level work.
Filing growth compares 2021 (25 records) with 2024 (62) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 260 records in scope (CR5), not by the ranked leaders only.
What the CXL memory pooling patent record shows
Compute Express Link memory pooling and disaggregated memory patents sit at the intersection of processor interconnect design and memory management, and the record here spans 260 patent families filed between 2015 and mid-2026. Filing activity was effectively absent before 2017 and built steadily through the early 2020s, reaching a peak of 62 families in 2024. Because publication typically lags filing by around eighteen months, the most recent year’s count of 9 understates actual filing activity rather than signalling a real drop-off.
The bulk of the activity is filed through the United States Patent and Trademark Office, with the European Patent Office and the WIPO PCT route each contributing a meaningful secondary share. Filings into China, India and South Korea remain small by comparison, which matters for anyone assessing freedom to operate regionally rather than globally.
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Filing trend and technology composition
The two views below separate timing from subject matter: when filings were made, and which IPC subclasses carry the claims.
Filing trend (2017–2026)
Filings ramped from zero in 2017 to a peak of 62 in 2024, passing through 43 at the 2022 midpoint. The partial count of 9 for 2026 reflects the publication lag rather than a genuine collapse in filing.
IPC subclass composition
Every record in the corpus carries a G06F classification, confirming the search is anchored correctly on core data-processing and memory management. H04L (26), H04W (14) and G06N (12) records show meaningful but secondary overlap with networking, wireless and AI-adjacent claims, while G11C (2) and H01R (3) remain marginal — the physical memory-cell and connector layers are largely unclaimed in this corpus.
Shares are the percentage of the 260 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on CXL Memory Expansion and Pooling with Eureka
This page is one run against one query. Ask Eureka your own question about cxl memory expansion and pooling and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited and representative filings
Memory Pooling and Sharing Enabling Scalable LLM Inference over Scaleup AI Fabrics (US20260056904A1)
The filing introduces a Resource Provisioning Unit that performs host-to-host physical address translation, letting external hosts access shared DRAM over CXL protocols. It combines CXL.mem access through Host-managed Device Memory regions with CXL.io transaction handling, positioning memory pooling explicitly for large-model inference workloads rather than generic server consolidation.Filed by UNIFABRIX LTD., published 2026-02-26.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20210132999A1 | Inter-server memory pooling | 67 |
| 2 | US20110246742A1 | Memory pooling in segmented memory architecture | 54 |
| 3 | US20220004488A1 | Software drive dynamic memory allocation and address mapping for disaggregated memory pool | 38 |
| 4 | US20240378161A1 | Port-based routing (PBR) switches, compute express link (CXL) fabric, and CXL switch to manage cache coherenc… | 28 |
| 5 | US20230017643A1 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch soc | 28 |
| 6 | US20220114125A1 | Low-latency optical connection for CXL for a server CPU | 27 |
| 7 | US20230236995A1 | Techniques to share memory across nodes in a system | 24 |
| 8 | US11388268B1 | Network systems and methods for CXL standard | 24 |
| 9 | US20230022544A1 | Transactional memory support for compute express link (CXL) devices | 23 |
| 10 | US20230027178A1 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch soc and… | 23 |
Citation counts favour older filings that have had more time to accumulate citations within the searched corpus; treat them as a marker of influence on subsequent filers, not of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three patterns stand out once family counts, citation weight and filing timing are set side by side.
A single dominant filer is already pulling back
The assignee with the most recent-year filings (5) also shows the sharpest year-over-year decline, down 75%. Most other active assignees in the momentum table sit at one filing or zero, with several other large players flat at 0% change from a base of zero. That pattern looks like an early, concentrated filing push that has already passed its peak intensity rather than a field still accelerating.
Foundational pooling claims still anchor the field
The most-cited record, on inter-server memory pooling, sits well ahead of newer filings on coherence and fabric switching. Because citation counts accumulate over time, this reflects influence on the field's vocabulary and architecture more than current commercial weight — newer CXL-switch and coherency filings are catching up in citation count despite far less time in the corpus.
Claims sit almost entirely in core data processing
Every record in the corpus touches G06F, and the next largest subclass, H04L, appears in only 26. That gap indicates the network-fabric and wireless-integration aspects of CXL pooling are comparatively open, even though the core memory-management architecture is densely claimed.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to cxl memory expansion and pooling, with the prior art for and against each one.
Who is filing, and where the field is still open
Filing activity is concentrated among a small set of assignees, with collaboration between them still rare in this dataset.
UNIFABRIX
The most active assignee in the most recent year, but its own year-over-year decline of 75% suggests a front-loaded filing strategy around its resource-provisioning and memory-sharing architecture rather than a steadily growing programme.
Intel and PANMNESIA
Both hold a single filing in the latest year with no change from the prior year — consistent with incumbents maintaining a baseline presence in CXL memory claims rather than expanding it.
Micron and Samsung
Both show a full drop to zero filings in the latest year after prior activity, which given publication lag may understate work already filed but not yet published, rather than confirming an actual halt.
| Assignee | Recent year | YoY |
|---|---|---|
| UNIFABRIX LTD. | 5 | -75% |
| Intel Corporation | 1 | 0% |
| PANMNESIA INC | 1 | 0% |
| Micron Technology, Inc. | 0 | -100% |
| Samsung Electronics Co., Ltd. | 0 | -100% |
| ELASTICS CLOUD INC | 0 | — |
| Dell Products L.P. | 0 | — |
| Advanced Micro Devices, Inc. (AMD) | 0 | — |
Where to look next
The filing and citation data point to specific next steps depending on whether the goal is freedom-to-operate or identifying open claim space.
Check coherence and switching claims closely
Recent high-cited filings on CXL switch fabric and cache coherency management are climbing fast in citation count despite short time in the corpus, signalling where competitive attention is shifting.
Explore coherence claims in EurekaMap the co-assignee network
Collaborative filing between assignees is rare in this corpus — the strongest pairing recorded is a single university-industry pair — so most claim territory is still held by single entities.
Trace assignee relationships in EurekaWatch the connector and memory-cell layers
H01R and G11C classifications appear in only a handful of records each, leaving the physical connector and memory-cell implementation layers comparatively open relative to the architecture layer.
Search white space in EurekaCommon questions on CXL memory patents
Filing is concentrated but not dominated by one long-standing leader. In the most recent year, UNIFABRIX filed the most (5), though that figure is down 75% from the year before, while established players such as Intel and PANMNESIA each hold a single recent filing at flat year-over-year activity. Micron and Samsung both show zero filings in the latest year after prior activity, which given the roughly 18-month publication lag may not yet reflect work already filed. No single assignee holds a commanding, sustained share across the full 260-family corpus.
Not clearly, based on the trend so far. Filings rose from zero in 2017 to a peak of 62 in 2024, passing through 43 at the 2022 midpoint, but the pace from 2022 to 2024 was not a sharp acceleration and the most recent partial year sits at only 9. Because publication lags filing by about 18 months, the true 2025-2026 count is understated, but the shape of the curve through 2024 already looks like a plateau rather than continued exponential growth.
Every record in this corpus is classified under G06F, covering electric digital data processing and confirming the corpus sits squarely in memory and processing architecture. Secondary overlap comes from H04L (digital information transmission, 26 records) and H04W (wireless communication networks, 14 records), with a smaller AI-computing overlap under G06N (12 records). Connector-level (H01R) and static memory (G11C) classifications appear in only a handful of records, marking those as comparatively open areas relative to the core architecture claims.
This UNIFABRIX filing, published February 2026, describes a Resource Provisioning Unit that performs host-to-host physical address translation so that external hosts can access shared DRAM using CXL protocols, combining CXL.mem access through Host-managed Device Memory regions with CXL.io transaction handling. It is explicitly framed around scaling large language model inference across AI fabrics rather than general server memory consolidation. Anyone building host-to-host memory sharing for AI inference workloads over CXL should review its specific claim language on address translation and HDM region management before designing a similar mechanism.
The clearest gaps sit outside the core G06F architecture claims that cover all 260 records: fabric-level switching and cross-host coherence protocols are represented but thinner than the core memory-management layer, and the physical connector layer (H01R, 3 records) and memory-cell level implementations (G11C, 2 records) are barely claimed at all. Wireless-integrated pooling architectures also show only light overlap (H04W, 14 records) relative to the wired, data-centre-centric filings that dominate the corpus. These are the branches worth checking first before assuming a proposed claim is already occupied.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.