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Run your analysis now →https://www.patsnap.com/resources/blog/rd-blog/deep-silicon-etch-for-mems-structures-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Patent Landscape · MEMS FabricationDeep Silicon Etch for MEMS Structures: Patents Behind Sidewall Control and Aspect-Ratio Etching
- 28.0% concentration at the top. The top 5 of 343 records account for 96 filings (28.0%), with the leader alone holding 21 — a narrow group controls a meaningful share of documented etch-control art.
- Filing momentum has cooled since 2021. Filings fell from 13 in 2021 to 6 in 2024, a 54% drop over that span — the last complete filing years available given publication lag.
- Claims cluster in semiconductor devices, not MEMS proper. 53.1% of records sit in H01L (semiconductor devices) versus 16.9% in B81C (MEMS manufacturing), showing etch-control claims are filed adjacent to the device layer more than the MEMS process class itself.
343
Published Records
28%
Top-5 Share of All Records
-54%
Filing Growth 2021→2024
US
Leading Jurisdiction
Filing growth compares 2021 (13 records) with 2024 (6) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 343 records in scope (CR5), not by the ranked leaders only.
Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Overview
What this landscape covers
Deep reactive ion etching (DRIE) and related deep silicon etch processes are the workhorse steps for cutting high-aspect-ratio trenches, probe arrays and optical structures into silicon. The claims in this dataset concentrate on the control problems that make or break a wafer run: sidewall verticality, notching at the buried oxide interface, scallop roughness on trench walls, mask undercut, and uniformity across the wafer as aspect ratio increases. These are process-control claims layered on top of a well-known etch chemistry, which is why they show up as heavily in semiconductor-device and optics classes as in the MEMS manufacturing class itself.
The 343 records in scope span 2015 through the 2026 cut-off, with United States, EPO and PCT filings dominating the receiving-office mix. Because publication lags filing by roughly 18 months, the most recent one to two years understate real filing activity and should be read as provisional.
Filing activity and technology composition, 2015–2026
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
The Data
Filing trend and technology composition
Two views of the same 343-record corpus: how filing activity has moved year over year, and which IPC subclasses the claims actually sit in.
Filing trend, 2017 peak to present
Filings peaked at 20 in 2017. Activity has since cooled, with 2021 at 13 falling to 6 by 2024 — a 54% drop over that three-year span, the last window unaffected by publication lag. 2025 and 2026 figures are still filling in and should not be read as a continued decline.
Where the claims sit across IPC subclasses
H01L (semiconductor devices) covers 53.1% of the 343 records, well ahead of G02B (optical elements, 19.5%) and B81C (MEMS manufacturing, 16.9%). Because a single record can carry several IPC classes, these shares sum to more than 100% and should be read individually, not added together.
Shares are the percentage of the 343 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.
Go deeper on Deep Silicon Etch for MEMS Structures with Eureka
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The prior art shaping this field
Representative Filing
US11850416B2 — Method of manufacturing a probe array
THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Filed by The Regents of the University of Michigan and granted 2023-12-26, this patent describes DRIE-etched ultra-high-aspect-ratio holes in silicon, refilled with multiple films to form high-density probe arrays for neural-based applications. It uses a DRIE lag-effect technique to control tip sharpness and electrode length, producing narrow, long, dense needles side by side in a single array, including multimodal arrays with mixed recording and stimulation sites.Selected as representative because it packages several of the field's core control problems — aspect-ratio-dependent etch lag, tip geometry, array density — into a single granted claim set.
Most-cited records in scope
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20100173494A1 | Method and apparatus for anisotropic etching | 157 |
| 2 | US6328482B1 | Multilayer optical fiber coupler | 142 |
| 3 | US20020166838A1 | Sloped trench etching process | 141 |
| 4 | US20050110157A1 | Device package and method for the fabrication and testing thereof | 107 |
| 5 | US7129163B2 | Device package and method for the fabrication and testing thereof | 99 |
| 6 | US20100213579A1 | Methods for fabrication of high aspect ratio micropillars and nanopillars | 88 |
| 7 | US20050037608A1 | Deep filled vias | 84 |
| 8 | US20050111797A1 | Device package and methods for the fabrication and testing thereof | 78 |
| 9 | US7508065B2 | Device package and methods for the fabrication and testing thereof | 71 |
| 10 | US20100136281A1 | Dry adhesives and methods for making dry adhesives | 68 |
Citation counts favour older records inside any searched corpus — treat this table as a map of foundational influence, not of current filing activity.
Each row carries its publication number; clicking a row searches Eureka by that number.
Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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What the numbers mean for a filing decision
Three readings of the same corpus: how concentrated the field is, where filing activity is heading, and which patents actually anchor the prior art a new filing has to clear.
Concentration
28.0%
of 343 records held by the top 5 assignees
A narrow group, not a monopoly
The leader holds 21 records and fifth place holds 15, out of 343 total. That is meaningful concentration but well short of a lockout — the top 10 combined reach 45.8%, leaving more than half the field to a long tail of single- and few-filing entrants.
Top 10 combined: 157 records, 45.8% of all records in scope.
Momentum
-54%
filing change, 2021 to 2024
Activity has cooled from its 2017 peak
Filings peaked at 20 in 2017 and had fallen to 13 by 2021, then to 6 by 2024 — a 54% drop over that three-year window. Treat 2025 and 2026 counts as incomplete rather than as evidence the decline is continuing.
Peak year: 2017 at 20 filings; 2024 is the last complete year available.
Composition
53.1%
of records classed under H01L
Etch-control claims sit closer to the device than the process
More than half of records fall in H01L (semiconductor devices), versus 16.9% in B81C (MEMS manufacturing proper). Claims describing etch uniformity and sidewall control are being filed as device-integration art, not as standalone process patents.
G02B (optical elements) and H01S (lasers) together account for a further meaningful share, reflecting DRIE's use in photonic and optical MEMS structures.
Eureka AI Agent
Looking for what nobody has claimed yet?
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to deep silicon etch for mems structures, with the prior art for and against each one.
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Who's Filing
Assignee landscape and collaboration patterns
The ranking covers 100 companies returned by the data endpoint, counted in records — not a top-50 or top-100 cut, just the full ranking the search returns.
Leader
21 records
single largest assignee
One clear leader, no runaway gap to the field
The top-ranked assignee holds 21 of the 343 records, roughly a third more than fifth place at 15 and nearly double tenth place at 11 — a gradual taper rather than a cliff.
Top 5 combined: 96 records, 28.0% of all records in scope.
Long tail
100 ranked
assignees in the full ranking
Most of the field files rarely
Beyond the top 10, filing counts drop quickly. This is typical of a process-control niche: academic groups, instrument makers and foundries each contribute a handful of records rather than sustained portfolios.
Top 10 combined: 157 records, 45.8% of all records in scope.
Collaboration
10 pairs
co-assignee pairings identified
Inventor-level clustering around a small academic group
The strongest co-assignee links are inventor pairs rather than corporate joint filings, with one inventor appearing across all three strongest pairings — a signature of a university lab filing repeatedly with different collaborators rather than a corporate alliance.
Strongest pairs each co-appear on 6 records.
Recent-year filing momentum by assignee
| Assignee | Recent year | YoY |
|---|---|---|
| WIT-A Sensing Technology Co., Ltd. | 0 | — |
| Rohm and Haas Electronic Materials LLC | 0 | — |
| Nanohenry Inc. | 0 | — |
| Nuvotronics Inc. | 0 | — |
| Microsaic Systems PLC | 0 | — |
| Lam Research Corp. | 0 | — |
| Board of Regents, The University of Texas System | 0 | — |
| Massachusetts Institute of Technology | 0 | — |
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's Next
Where to take this analysis
The dataset points to a field with real but not overwhelming concentration, cooling recent filing activity, and process-control claims spread across several adjacent IPC classes rather than parked in one place.
Map your own claim language against the leaders
Run your specific etch-control approach — sidewall angle, scallop depth, mask-undercut tolerance — against the top assignees' granted claims to see where a new filing would actually add scope.
Explore assignee claims in EurekaTrack the white-space branches before they fill in
Sub-areas like notching mitigation and multimodal probe integration show thinner filing density now; that gap narrows as the broader field's activity resumes past the current publication-lag window.
Monitor emerging filings in EurekaSource: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ
Common questions about deep silicon etch patents
This dataset covers patents and applications describing deep reactive ion etching, deep silicon etch, or deep trench etching processes, combined with claims about sidewall verticality, notching effects, aspect-ratio-dependent etching, scallop roughness, mask undercut, or uniformity across the wafer. It excludes general silicon etch patents that do not address these specific process-control problems. The 343 records span 2015 through the 2026 data cut-off across multiple receiving offices, led by the United States, EPO and WIPO/PCT.
The ranking returned by the dataset covers 100 assignees, with the single leading assignee holding 21 of the 343 records in scope. The top 5 assignees combined hold 96 records, or 28.0% of the field, while the top 10 combined hold 157 records, 45.8% of the total. That leaves more than half the field distributed across a long tail of assignees with only a handful of filings each, including universities, instrument makers and specialist MEMS foundries.
Filing activity peaked in 2017 at 20 records and has since cooled: the last fully comparable window shows 13 filings in 2021 falling to 6 by 2024, a 54% decline over that three-year span. Because publication typically lags filing by around 18 months, 2025 and 2026 counts in the raw data are still incomplete and should not be read as evidence the decline is continuing or accelerating. A clearer read on the most recent years will only be available once those cohorts finish publishing.
Relative to the core etch-control claims, several adjacent branches show thinner filing density: scallop-roughness suppression techniques, notching mitigation specifically at the buried oxide interface, fine-grained aspect-ratio-dependent etch lag control, multimodal probe array integration, and wafer-edge uniformity correction. These are not gaps in the sense of being unclaimed outright, but areas where the density of granted claims is noticeably lower than in mainstream sidewall-verticality and mask-undercut claims, which is where a well-drafted new filing is more likely to find open scope.
The most-cited records in this dataset include foundational anisotropic-etching and sloped-trench-etching patents along with device-packaging patents tied to etch processes, some cited well over 100 times. High citation counts inside a searched corpus tend to favour older, foundational filings simply because they have had longer to accumulate citations, so this list is best read as a map of influential prior art rather than a signal of which technology is currently most active or valuable.
Answers are grounded in the same dataset. Derived from a Patsnap search on Deep Silicon Etch for MEMS Structures covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.