Design Verification Patents: Who Leads, Where the Gaps Are 2026
- Filing activity has plateaued, not grown. the field peaked at 10 families in 2022 and has not exceeded that since, despite ongoing filing through 2026.
- The most-cited art is old. the five highest-cited records date to the late 1990s and early 2000s, and still anchor emulation-based design verification claims cited well over 100 times.
- Filing is concentrated in one office. United States receives more than half of all filings (49 of 89), with South Korea and China a distant second and third.
Filing growth compares 2021 (6 records) with 2024 (5) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 89 records in scope (CR5), not by the ranked leaders only.
What this patent set covers
Design verification and formal methods patents cover the tools and techniques used to confirm that a chip design behaves as intended before it is fabricated: simulation-based verification, formal and equivalence checking, constrained-random testbenches, and hardware emulation aimed at closing coverage gaps. The dataset pulls 89 patent families filed between 2015 and 2026 that combine design-verification terminology with claim-level language on coverage closure, assertions, equivalence checking, constrained-random methods or emulation, restricted to IPC classes covering digital data processing, error detection and simulation modelling.
Because publication typically lags filing by around eighteen months, the 2025 and 2026 figures in any trend line understate actual filing activity for those years; the plateau described below is measured against 2022, which is far enough back to be reliably complete.
Filing trend and technology composition
Two views of the same 89-family dataset: how filing volume has moved year over year, and which IPC subclasses the claims actually sit in.
A flat trajectory since the 2022 peak
Filings rose from 3 in 2017 to a peak of 10 in 2022, then held roughly level rather than continuing to climb. A dataset that peaks mid-window and does not exceed that peak in later (complete) years points to a technology area where the core claim space was staked out early, with incremental rather than expansive filing since.
Concentrated in core digital design and measurement classes
Every record in the set touches G06F (electric digital data processing), and a substantial secondary cluster of 25 records also touches G01R (electric and magnetic measurement), reflecting emulation and test-signal verification claims. AI-assisted verification (G06N), semiconductor device claims (H01L) and other adjacent classes appear only in single digits, marking them as emerging rather than established claim territory.
Shares are the percentage of the 89 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Design Verification and Formal Methods with Eureka
This page is one run against one query. Ask Eureka your own question about design verification and formal methods and every answer comes back with the patent numbers behind it.
Try EurekaThe patents anchoring this field
Performing transformer-based design verification for coverage closure in processor devices
Filed by Microsoft Technology Licensing and published February 2026, this application trains an online decision transformer using regression-testing trajectories from a design-under-test, then runs an online learning phase where the model generates action sequences aimed at maximizing coverage and receives observed states and coverage metrics back from a testbench environment.It is the newest record in the dataset and illustrates where verification claims are heading: coverage closure driven by a learned policy rather than hand-written constrained-random rules.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US5841967A | Method and apparatus for design verification using emulation and simulation | 139 |
| 2 | US6141630A | System and method for automated design verification | 111 |
| 3 | US6058492A | Method and apparatus for design verification using emulation and simulation | 104 |
| 4 | US6182248B1 | Method and tool for computer bus fault isolation and recovery design verification | 78 |
| 5 | US6687662B1 | System and method for automated design verification | 53 |
| 6 | US6698003B2 | Framework for multiple-engine based verification tools for integrated circuits | 39 |
| 7 | US20130055022A1 | Flexible soc design verification environment | 21 |
| 8 | US8639981B2 | Flexible SoC design verification environment | 14 |
| 9 | US20060156145A1 | Using patterns for high-level modeling and specification of properties for hardware systems | 13 |
| 10 | KR100812938B1 | Debugging Apparatus Using Both Very Large Scaled Digital System Realized in Hardware and Simulation, and Debu… | 13 |
Citation counts favour older filings simply because they have had more time to accumulate citations within the corpus; treat them as a measure of influence on later filings, not of present-day relevance.
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Three read-throughs from the trend, the citation table and the IPC split, aimed at where new claims still have room to land.
Growth has stalled, not accelerated
A midpoint-year peak that later years have not exceeded suggests the foundational emulation and coverage-closure claims were largely staked out by the early 2020s. New entrants are more likely to succeed by combining verification methods with adjacent techniques (AI-driven test generation, for instance) than by re-filing on the core methods.
Foundational emulation patents still anchor the field
The most-cited records in this set, several from the late 1990s, describe emulation-and-simulation-based design verification and automated verification systems. Their continued citation weight signals that later filings build on these methods rather than displacing them, which matters for freedom-to-operate review on any emulation-adjacent claim.
Measurement-linked verification is a distinct sub-cluster
Records that pair G06F with G01R point to a sub-cluster focused on signal- and measurement-based verification, likely tied to emulation hardware rather than pure software simulation. This is a narrower, more hardware-dependent filing path than the general coverage-closure claims that dominate the rest of the set.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to design verification and formal methods, with the prior art for and against each one.
Assignees and where momentum sits
Filing here is led by the established EDA vendors, with recent-year momentum flat across the names tracked rather than shifting toward a new leader.
One recurring inventor-assignee pairing stands out
The strongest co-assignee link in the dataset pairs an individual inventor, Yang Sei Yang, with a corporate assignee across six shared families, well ahead of any other pairing. That concentration suggests a single research program rather than a broad multi-team effort behind those filings.
No assignee is currently accelerating
Every assignee tracked for recent-year momentum, including major EDA vendors, shows zero families in the latest year, with at least one showing a full year-over-year decline. Read alongside the publication lag, this likely reflects filings still in the pipeline rather than an actual stop in R&D, but it means the public record currently shows no single company pulling ahead.
Filing strategy still centres on the US
More than half of all families in this set were filed at the United States receiving office, with South Korea and China each in the low double digits or fewer. A verification-technology filer without US coverage is missing the office where the bulk of enforceable claims in this field currently sit.
| Assignee | Recent year | YoY |
|---|---|---|
| Quickturn Design Systems | 0 | — |
| YANG SEI YANG | 0 | — |
| Cadence Design Systems | 0 | — |
| Mentor Graphics | 0 | — |
| Synopsys, Inc. | 0 | -100% |
| Yang Sei Yang | 0 | — |
| SciFive, Inc. | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
Where to take this analysis
The dataset points to a mature core and a thin edge of AI-assisted verification claims. Two directions are worth following up before committing a filing strategy.
Model the white space in AI-assisted coverage closure
Only a handful of records in this set touch G06N, yet the most recent representative filing is exactly this kind of AI-driven coverage-closure claim. Mapping that thin cluster against the dense G06F core shows where a new claim has room.
Explore white space in EurekaTrack the assignees showing zero recent momentum
Every major assignee in this set shows no filings in the latest tracked year. Given the publication lag, watching for a rebound in the next reporting cycle will show whether this is a real slowdown or a pipeline gap.
Set up assignee monitoring in EurekaCommon questions on design verification patents
In this dataset, a design verification patent is one whose claims combine design-verification terminology, such as simulation-based or formal verification, with specific technical mechanisms like coverage closure, assertions, equivalence checking, constrained-random test generation, or emulation. It is a narrower category than general EDA patents because it requires both the verification framing and one of these specific mechanisms to appear at the claim level, not just in background text. This is why the set totals 89 families rather than the much larger number of patents that merely mention verification in passing.
The trend data shows filings rising from 3 in 2017 to a peak of 10 in 2022, then holding roughly level rather than climbing further in the years since. A plateau after a mid-window peak usually means the core methods, here emulation-based and simulation-based verification, were substantially claimed early, so later filers are adding narrower or adjacent claims rather than filing foundational ones. Note that the most recent one to two years in any trend are undercounted because patent publication lags filing by about eighteen months, so the true 2025 and 2026 numbers will end up higher once those applications publish.
The most-cited records in this dataset, several exceeding 100 citations, describe emulation-and-simulation-based design verification methods and automated verification systems dating from the late 1990s and early 2000s. High citation counts in a search corpus like this one tend to favour older patents simply because they have had more time to accumulate citing references, so they signal historical influence on how the field developed rather than which company is most active today. For current activity, filing volume and recent-year momentum are the more relevant signals, and neither points to a single company currently pulling ahead.
Yes, particularly at the intersection of verification and machine learning. The IPC composition shows only a handful of records touching G06N (AI-based computing) against 89 touching G06F, and the most recent representative filing in the set is precisely this kind of transformer-driven coverage-closure method. That imbalance, a large established core and a thin AI-assisted edge, is the clearest sign of open claim space in this field.
The United States dominates, receiving 49 of the 89 families in this dataset, more than the next several offices combined. South Korea (11) and China (6) follow, with WIPO PCT filings, the EPO and Israel each in single digits. A company building a defensive or offensive patent position in this field needs US coverage as the baseline, with South Korea and China as the next-priority jurisdictions depending on where its competitors manufacture or design.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.