Domain-Specific AI Accelerator Patents: Leaders & Trends 2026
- Filing is still accelerating, rising from a single family at the 2022 midpoint to a peak of 10 in 2024, with 2026 already partial.
- The field spans far beyond chip design, with G06F and G06N each carrying 9 records while healthcare informatics, alarm systems and wireless transmission subclasses each pick up a handful of filings.
- No single assignee dominates, recent-year momentum shows most tracked assignees at zero new filings in the latest year, leaving the field open to new entrants.
What this landscape covers
Domain-specific AI accelerator architecture concerns hardware and firmware built to execute machine learning workloads more efficiently than general-purpose processors — dataflow mapping, on-chip memory management, compiler support and energy-per-inference optimisation are the recurring claim elements in this dataset. The search spans tensor processing units, in-memory compute designs and edge inference accelerators, filtered against IPC classes covering AI-based computing, digital data processing and general computer architecture.
The 16 families tracked here sit at the intersection of chip architecture and applied AI, with meaningful overlap into edge computing, wearable diagnostics and industrial signalling — a sign that accelerator claims are increasingly drafted around a specific deployment context rather than the chip alone.
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Filing trend and technology composition
Two views of the same 16-family dataset: how filing activity has moved year over year, and which IPC subclasses the claims actually sit in.
Accelerating, from a low base
Filings moved from zero in 2017 to a peak of 10 in 2024, with the 2022 midpoint at just 1 family. Because publication typically lags filing by around 18 months, the 2026 figure of 3 is a partial count, not a slowdown.
Split across compute and application domains
G06F (digital data processing) and G06N (AI-based computing) each carry 9 of the 16 records, the expected core. The remainder — healthcare informatics, alarm and signalling systems, wireless transmission — shows accelerator claims increasingly drafted for a specific edge or embedded deployment rather than as standalone chip architecture.
Shares are the percentage of the 16 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
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Try EurekaRepresentative filing and most-cited records
Tensor processing unit with configurable hardware
Various embodiments described herein dynamically control circuitry in a tensor processing unit (TPU) to efficiently cause arithmetic logic units (ALUs) to perform artificial intelligence (AI)-based operations, such as those involving matrix-matrix operations. Circuitry in the TPU is controlled based on a determination that ALUs are arranged to perform certain dot product operations over a plurality of clock cycles and that a subset of ALUs do not perform a dot product operation during a first clock cycle of the plurality of clock cycles. Controlling the circuitry in the TPU causes the TPU to repurpose the ALUs to cause at least a portion of the subset of ALUs to perform, during the first clock cycle, other operations.Filed by Microsoft Technology Licensing, published 2025-10-02.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20250009237A1 | Edge computing system with low power wide area network connectivity and autonomous or semi-autonomous machine… | 7 |
| 2 | CN119201836A | 基于RISC-V架构的存内计算AI加速器设计架构及控制方法 | 5 |
| 3 | US20230185531A1 | Multiply-accumulate with broadcast data | 4 |
| 4 | US20250045240A1 | Approximate computing based tensor processing unit (APTPU) | 3 |
| 5 | US12290339B2 | Edge computing system with low power wide area network connectivity and autonomous or semi-autonomous machine… | 2 |
| 6 | CN121542216A | 用于张量处理单元的张量维度重组方法及装置、芯片 | 1 |
| 7 | CN119441698A | 张量处理单元上加速稀疏矩阵计算的方法及存储介质 | 1 |
| 8 | CN116306846A | 一种采用SIMD与SIMT结合的AI加速器架构方法 | 1 |
Citation counts reflect influence within the searched corpus and skew toward older records; treat them as a signal of prior relevance, not current market weight.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Publication numbers are shown where the record carries one (8 of 8 rows); clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three data points that change how a team should read this landscape before drafting or clearing claims.
Growth is recent and still building
The jump from a single family at the 2022 midpoint to 10 in the peak year means most of the claim space was staked out in the last three to four years. Prior art searches that stop at 2020 will miss the bulk of relevant filings.
Influence clusters on edge-deployment claims
The most-cited record in this set concerns an edge computing system with low-power wide-area connectivity and autonomous machine learning, not a pure chip-architecture claim — citation weight here favours system-level integration over isolated accelerator design.
Filing is split across two primary offices
The United States and China each account for a substantial share of receiving-office activity, with India and WIPO PCT filings adding a smaller but present international layer — freedom-to-operate work needs to clear both major jurisdictions, not just one.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to domain-specific ai accelerator architecture, with the prior art for and against each one.
Who is filing, and where the gate sits
Recent-year momentum shows a field without an entrenched leader: most tracked assignees, including well-resourced ones, show zero new filings in the latest year, while at least one specialist entrant is still active.
A narrow window of current activity
Only one tracked assignee, a specialist in-memory-compute accelerator firm, shows a filing in the latest year among the assignees with recent-year momentum data; the rest — including a major US software licensor and an Indian university — show none in that window.
Academic filing sits alongside corporate activity
Galgotias University appears among tracked assignees, indicating this is not a purely corporate field — academic groups are staking claims in accelerator architecture alongside chip vendors and software licensors.
Filers are targeting adjacent deployment contexts
Assignees are not confining claims to chip architecture alone; healthcare informatics, wearable diagnostics and industrial signalling subclasses each carry filings, suggesting accelerator IP is being drafted with a specific end application in mind.
| Assignee | Recent year | YoY |
|---|---|---|
| Suzhou Yizhu Intelligent Technology Co., Ltd. | 1 | — |
| Mozi Technology Holdings Co., Ltd. | 0 | — |
| GALGOTIAS UNIVERSITY | 0 | — |
| CAREBAND INC | 0 | — |
| Hangzhou Weina Hexin Electronic Technology Co., Ltd. | 0 | — |
| Microsoft Technology Licensing, LLC | 0 | — |
| Flex Logix Technologies, Inc. | 0 | — |
| SambaNova Systems, Inc. | 0 | -100% |
Where to take this analysis
The dataset points to open claim space rather than a settled field. These are the logical next steps for a team acting on it.
Map the white space before drafting
The under-claimed sub-areas identified here — in-memory compute control, approximate tensor units, edge compiler scheduling — are candidates for a first claim rather than a crowded one. Confirm thin coverage against the full family text before committing drafting resources.
Explore white space in Eureka →Track the specialist filers, not just the large names
Recent-year momentum sits with a narrower set of specialist entrants rather than the largest assignees by historical volume. Watching filing cadence from these smaller players will surface shifts earlier than watching the incumbents.
Set up assignee monitoring in Eureka →Clear the most-cited system-level claims first
The highest-citation records in this set concern system-level edge deployment, not isolated chip design — freedom-to-operate review should prioritise these before narrower architecture claims.
Run a clearance search in Eureka →Common questions on this landscape
This dataset tracks 16 patent families published between 2015 and mid-2026, matched against a search string covering AI accelerator architecture, domain-specific accelerators and tensor processing units. Filing activity was negligible before 2022 and rose to a peak of 10 families in 2024. Because the 2026 count is still partial due to publication lag, the true recent total is likely higher once later filings publish.
No single assignee holds a commanding lead in this dataset; recent-year momentum shows most tracked assignees, including a major US software licensor, at zero new filings in the latest year. One specialist in-memory-compute accelerator firm shows continued activity. This distribution suggests the field is still open rather than consolidated around one or two dominant filers.
A domain-specific accelerator is architected around a narrow set of operations — typically matrix or dot-product arithmetic for neural network inference — rather than general instruction execution. Patent claims in this space concentrate on dataflow mapping, on-chip memory management, compiler support and energy-per-inference efficiency, all of which are optimisations that only make sense once the workload is fixed. General-purpose processors, by contrast, are claimed around flexibility across arbitrary instruction sets rather than efficiency on a fixed workload.
Based on the IPC composition and citation pattern in this dataset, thinner coverage sits in in-memory compute control logic, approximate or reduced-precision tensor processing, edge-device compiler scheduling and accelerator integration with low-power wide-area links. These branches carry filings but not the density seen in the core G06F/G06N compute claims, making them more viable for a first-mover claim than the crowded centre of the field.
Citation counts inside a searched patent corpus tend to favour older, more established records and system-level claims that later filings build on, rather than reflecting which technology is currently most active. In this dataset the top-cited record covers an edge computing system with low-power wide-area connectivity and autonomous machine learning — a system-level integration claim that newer, narrower accelerator architecture filings cite as background. This does not mean edge integration is more important today, only that it accumulated citations earlier.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.