DRAM Scaling and Architecture Patents: Trends & Leaders 2026
- 7,221 patent families span 2015-2026, with filing peaking at 143 in 2019 and declining since — the most recent years are undercounted due to publication lag.
- G11C dominates static and digital memory claims account for 6,269 of the tracked records, far ahead of manufacturing (H10B, 2,084) and general semiconductor devices (H01L, 2,015).
- Momentum has cooled sharply several tracked assignees, including Micron and Rambus, show 0 to -100% year-over-year filing activity in the latest tracked year.
What this landscape covers
This landscape tracks 7,221 patent families filed between 2015 and 2026 across DRAM cell architecture, capacitor scaling, refresh power, row hammer mitigation, sense amplifier design and high bandwidth memory. The search spans IPC classes G11C11, H01L27 and H01L21, capturing both the memory-specific circuit claims and the underlying semiconductor device and manufacturing claims that support them.
Filing activity peaked in 2019 and has since declined toward a partial, publication-lag-affected 2026 figure. The United States is the leading receiving office by a wide margin, followed by Japan, the European Patent Office and South Korea, reflecting where the core R&D and litigation exposure for this technology concentrates.
Filing trends and technology composition
Publication volume and IPC distribution across the 2015-2026 window show where DRAM scaling and architecture claims concentrate and how filing activity has moved since the 2019 peak.
Filing trend, 2017-2026
Filings rose to a peak of 143 in 2019, held near that level through the 2022 midpoint (136), and have declined since; 2026 is partial due to the roughly 18-month publication lag, so the most recent bars understate actual filing activity.
IPC subclass composition
G11C (static and digital memories) dominates at 6,269 records, with H10B (memory device manufacture) and H01L (semiconductor devices) each above 2,000 — confirming that most claim activity sits in core cell and sense-circuit design rather than downstream processing or measurement subclasses.
Shares are the percentage of the 7,221 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on DRAM Scaling and Architecture with Eureka
This page is one run against one query. Ask Eureka your own question about dram scaling and architecture and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative and most-cited filings
CMOS DRAM Cell with Sense Amplifier (US8934286B2)
A complementary metal-oxide-semiconductor (CMOS) DRAM cell pairs an NFET and a PFET around a shared storage capacitor, accessed through a pair of bit lines. Its sense amplifier uses a single-ended read path through only one bit line, and a data-dependent write-back path that selects which bit line writes back based on the stored logical value.Filed by Marvell Asia Pte, Ltd., priority date 2015-01-13.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6472266B1 | Method to reduce bit line capacitance in cub drams | 618 |
| 2 | US5638317A | Hierarchical DRAM array with grouped I/O lines and high speed sensing circuit | 556 |
| 3 | US20130003467A1 | Digit line comparison circuits | 515 |
| 4 | US6166942A | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines | 493 |
| 5 | US6563754B1 | DRAM circuit with separate refresh memory | 486 |
| 6 | US6544837B1 | SOI stacked DRAM logic | 477 |
| 7 | US5367488A | DRAM having bidirectional global bit lines | 463 |
| 8 | US6466499B1 | DRAM sense amplifier having pre-charged transistor body nodes | 450 |
| 9 | US6005799A | Methods and circuits for single-memory dynamic cell multivalue data storage | 440 |
| 10 | US5698869A | Insulated-gate transistor having narrow-bandgap-source | 440 |
Ranked by citation count within the searched corpus; older records accumulate more citations by virtue of age, so treat this as a signal of influence rather than current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Reading the trend, citation and co-filing data together points to where the DRAM architecture field is settled and where it is still open.
Growth has flattened, not stopped
Filings held near-peak through the 2022 midpoint (136) before declining, with the 2026 figure understated by publication lag. The pattern reads as claim space maturing rather than the technology losing relevance.
A handful of records anchor the field
The five most-cited records span capacitor scaling and sense-amplifier architecture, and their citation counts are an order of magnitude above typical records in the corpus — a sign of foundational claims that later filings had to navigate around.
Recent activity has cooled across the board
Samsung shows modest latest-year activity (2 filings) while Rambus, Micron, Hitachi, Mitsubishi Electric and IBM show flat or sharply declining counts — consistent with both publication lag and a genuine pullback from broad architectural filing.
Co-filing is limited and corporate-family driven
The strongest co-assignee pairs link parent companies to their own engineering subsidiaries, such as Hitachi with its VLSI systems affiliate, rather than reflecting cross-company joint development.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to dram scaling and architecture, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Hitachi, Ltd. | Hitachi ULSI Systems Co., Ltd. | 60 |
| Hitachi, Ltd. | Hitachi VLSI Engineering Corporation | 35 |
| Mitsubishi Electric Corporation | Mitsubishi Electric Engineering Company, Limited | 32 |
| Hitachi, Ltd. | Texas Instruments Incorporated | 26 |
| Toshiba Corporation | Toshiba Microelectronics Corporation | 22 |
| Fujitsu Limited | Fujitsu VLSI Limited | 22 |
| Hitachi, Ltd. | Hitachi Device Engineering Co., Ltd. | 17 |
| Hitachi, Ltd. | Elpida Memory, Inc. | 17 |
The strongest co-assignee links in this dataset connect parent firms to their own engineering or systems subsidiaries rather than independent collaborators, indicating internal R&D structuring more than cross-company alliances.
Assignees and filing patterns
Filing activity concentrates among established memory and semiconductor manufacturers, with corporate-family co-filing and a long tail of smaller entrants rather than broad cross-company collaboration.
Core cell and sense-circuit claims dominate
The bulk of filing activity sits in static and digital memory claims (G11C), where legacy assignees such as Hitachi, Mitsubishi Electric, Toshiba and NEC hold long-running families alongside more recent activity from Samsung, SK Hynix and Micron.
Broad architectural filing has cooled
Micron shows a -100% year-over-year change and Rambus -88%, while several Japanese assignees report zero latest-year filings — a mix of genuine slowdown and the roughly 18-month publication lag understating the true recent picture.
Co-filing stays within corporate groups
The strongest co-assignee relationships connect parent companies to their own engineering subsidiaries, such as Hitachi with its VLSI systems affiliate and Mitsubishi Electric with its engineering arm, rather than independent joint ventures.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. (Korea) | 2 | — |
| Rambus Inc. | 1 | -88% |
| Micron Technology, Inc. | 0 | -100% |
| Hitachi, Ltd. | 0 | — |
| Mitsubishi Electric Corporation | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Toshiba Corporation | 0 | — |
| NEC Corporation | 0 | — |
Where to take this analysis
The filing and citation data point to specific next steps for teams evaluating freedom to operate or new filing strategy in DRAM architecture.
Check claim overlap against top-cited prior art
Before filing in sense-amplifier or capacitor-scaling space, compare draft claims against the highest-cited records in this corpus, since they anchor much of the surrounding claim language.
Run a claim comparison in EurekaTrack assignee momentum before committing R&D
Recent-year filing declines across several major assignees may reflect a genuine pullback from broad architecture claims toward narrower, adjacent problems like refresh power.
Monitor assignee activity in EurekaExplore under-claimed measurement subclasses
G01R and H03K carry far less filing density than the G11C core, and both intersect with row-hammer and refresh-power claims already active in this dataset.
Search white space in EurekaCommon questions on DRAM scaling and architecture patents
Filing activity in this corpus is led by a group of established memory and semiconductor firms including Samsung Electronics, Hitachi, Mitsubishi Electric, and Micron, alongside co-filing clusters between Hitachi and its VLSI systems affiliates. No single assignee holds a dominant share of the 7,221 families tracked; the distribution shows concentration among a handful of large players plus a long tail of smaller filers. Recent-year momentum has slowed across most of these assignees, with several showing zero filings in the latest tracked year, partly reflecting publication lag rather than an actual halt in R&D.
Filings in this dataset rose to 143 in 2019, held roughly flat through 2022 at 136, and have fallen since, with 2026 showing only 9 filings so far. Part of this decline is a publication-lag artefact: patent applications typically publish about 18 months after filing, so the last one to two years in any trend chart are always undercounted. The flattening from 2019 to 2022 combined with the later drop suggests that core cell-architecture and sense-amplifier claim space had become heavily occupied, pushing filers toward narrower or adjacent claims rather than broad architectural ones.
Capacitor scaling patents address the physical and electrical challenge of shrinking the storage capacitor while maintaining charge retention, and they tend to sit under H10B (memory device manufacture) and H01L (semiconductor devices) in this corpus. Sense-amplifier patents instead cover the read and write-back circuitry that detects and restores the small voltage signal from that capacitor, and they concentrate under G11C. The most-cited record in this dataset, US6472266B1, is a capacitor-scaling patent, while several others in the top-cited group, including US5638317A and US6166942A, are sense-amplifier and I/O architecture patents — both branches are essential and well-documented, but they solve different engineering problems.
Row hammer is a DRAM reliability issue where repeatedly accessing one memory row causes electrical interference that can flip bits in physically adjacent rows. It appears in this corpus as a claim-description term alongside refresh-power and sense-amplifier topics, and it intersects with the smaller measurement-focused IPC subclasses such as G01R (145 records) and H03K (143 records) rather than the large core memory subclass. Because these subclasses carry meaningfully lower filing volume than G11C's 6,269 records, row-hammer mitigation circuitry represents a comparatively under-claimed area relative to the core cell and sense-amplifier architecture.
High cumulative filing volume (7,221 families since 2015) reflects that claim space is heavily occupied, not that the underlying technology has stopped evolving — dense prior art in a subclass just means new filers need to differentiate more carefully. The decline from the 2019 peak and near-zero recent-year momentum for several tracked assignees suggest a slowdown in broad architectural filing, but this coexists with continued activity in narrower areas like high-bandwidth memory and refresh-power management, which are called out explicitly in the search criteria. Practitioners should read the recent drop as a shift in where activity concentrates, not as evidence the field is closed.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.