Design Rule Checking Patents: Leaders, Trends & White Space 2026
Filing growth compares 2021 (32 records) with 2024 (34) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 786 records in scope (CR5), not by the ranked leaders only.
What the design rule checking patent record shows
Design rule checking (DRC) sits at the boundary between chip design and manufacturing: it verifies that a layout obeys the geometric constraints a fabrication process can actually build. The 786 records in scope span 2015 through the 2026 cut-off and cluster overwhelmingly under G06F (electric digital data processing), with smaller but persistent overlap into semiconductor devices (H01L) and photolithography (G03F). That split reflects how DRC has historically been claimed: as a software verification method layered on top of a physical process, rather than as a manufacturing step in its own right.
Filing activity has stayed close to flat rather than accelerating: 2021 to 2024 — the most recent year with a complete publication picture — moved from 32 to 34 records, a 6% rise over three years. That is a mature, steadily-tended field rather than a fast-growing one. Ownership is concentrated: the leading assignee alone accounts for 87 of the 786 records, and the top ten combined hold 51.8% of all records in scope, with a long tail of single- or few-filing entrants filling out the rest of the ranking.
Filing trends and technology composition
Publication counts by year and by IPC subclass, drawn from the 786 records in scope. Because a single record can carry more than one IPC class, the composition shares add up to more than 100%.
A steady, not surging, filing line
Annual publications ran from 25 in 2017 to a peak of 34 in 2024, the most recent year that can be treated as complete; 2025 and 2026 figures will continue to fill in as publication catches up with filing, typically an 18-month lag.
Software verification logic dominates the classification mix
G06F covers 87.7% of the 786 records, far ahead of H01L (17.8%) and G03F (10.2%); smaller clusters in H10D, H10W, H05K, G06T and G06N mark where DRC work touches device structure, packaging, imaging and AI-assisted checking respectively.
Shares are the percentage of the 786 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
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Try EurekaThe prior art anchoring this field
Techniques for Verifying Error Detection of a Design Rule Checking Runset (US20090187867A1)
A technique for verifying error detection of a design rule checking runset includes assigning first shapes for a first layer of an integrated circuit design to a first cell and assigning second shapes for a second layer of the integrated circuit design to a second cell. Design rule checking is then performed on the first and second cells. Whether the design rule checking runset is functioning properly is then determined based on whether an error is detected in the design rule checking of the first and second cells.Filed by International Business Machines Corporation, published 2009-07-23. The claim targets runset self-verification — checking whether the DRC tool itself is correctly flagging errors — rather than the layout being checked.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6470489B1 | Design rule checking system and method | 528 |
| 2 | US6370679B1 | Data hierarchy layout correction and verification method and apparatus | 502 |
| 3 | US6009251A | Method and system for layout verification of an integrated circuit design with reusable subdesigns | 458 |
| 4 | US6415421B2 | Integrated verification and manufacturability tool | 384 |
| 5 | US7155689B2 | Design-manufacturing interface via a unified model | 358 |
| 6 | US6063132A | Method for verifying design rule checking software | 355 |
| 7 | US6505327B2 | Generating an instance-based representation of a design hierarchy | 350 |
| 8 | US6282696B1 | Performing optical proximity correction with the aid of design rule checkers | 282 |
| 9 | US6732338B2 | Method for comprehensively verifying design rule checking runsets | 254 |
| 10 | US6745372B2 | Method and apparatus for facilitating process-compliant layout optimization | 244 |
Citation counts are drawn from a searched corpus and skew toward older filings; treat them as a measure of influence on later filers, not of current commercial relevance.
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Four read-outs from the ranking, the trend line and the classification mix, aimed at where to file, who to watch and what is already occupied.
Ownership sits at the very top
The leading assignee alone holds 87 records, and the top five combined take 38.2% of all 786 records in scope. Below tenth place (13 records) the ranking thins into a long tail of occasional filers, which is where freedom-to-operate work should focus rather than on displacing the leaders.
A mature field, not a fast-growing one
Publications moved from 32 in 2021 to 34 in 2024, the last year with a reasonably complete count. That is a flat-to-slightly-rising line, consistent with DRC being a settled verification discipline rather than an emerging one.
Software claims dominate over process claims
G06F (digital data processing) appears on 87.7% of the 786 records, versus 17.8% for H01L and 10.2% for G03F. DRC is being claimed chiefly as computational verification logic; process-integration and photolithography framing remain comparatively thin.
The US is the primary filing venue
United States filings (446) lead by a wide margin ahead of China (109), Japan (61), WIPO PCT filings (59) and the EPO (31), indicating that most applicants still treat the US as the first or primary jurisdiction for DRC protection.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to eda & chip design: design rule checking patent landscape, with the prior art for and against each one.
Where to take this analysis
The ranking, the trend and the classification split each point to a different next step depending on whether the goal is freedom-to-operate, licensing, or identifying open claim space.
Map freedom-to-operate against the leaders
With 51.8% of all 786 records held by the top ten assignees, a new filing in core DRC logic is likely to sit near existing claims from those firms. Run a claim-by-claim comparison before drafting.
Explore assignee claims in EurekaTest under-claimed branches for white space
G03F, H10D and G06N each cover a small share of the 786 records despite touching adjacent, active problems — photolithography interaction, device-level structure and AI-assisted checking. Each is a candidate for a narrower, more defensible first claim.
Search white space in EurekaTrack the oldest anchor claims
The most-cited records, led by US6470489B1 at 528 citations, are two decades old and still shape how later filings are worded. Confirm their claim scope before assuming a design-around is clean.
Review cited prior art in EurekaCommon questions on the design rule checking patent landscape
The assignee ranking for this dataset is led by a single company with 87 of the 786 records in scope, well ahead of the fifth-ranked assignee at 40 and the tenth-ranked at 13. The top five combined hold 38.2% of all 786 records, and the top ten hold 51.8%, so ownership is concentrated at the very top before thinning into a long tail of occasional filers. This pattern is typical of a mature EDA sub-field where a small number of tool vendors and foundries have filed continuously for years.
Filings have been roughly flat rather than clearly accelerating: annual publications ran from 25 in 2017 up to a peak of 34 in 2024, a rise of 6% between 2021 and 2024 alone. Counts for 2025 and 2026 look lower in the raw data, but that is an artefact of publication lag — filings typically take about 18 months to appear in the record — not a real slowdown. Treat 2024 as the most recent complete year when judging the trend.
The overwhelming majority, 87.7% of the 786 records, carry the G06F classification for electric digital data processing, reflecting DRC's framing as a software verification method. Semiconductor devices (H01L) appear on 17.8% of records and photolithography (G03F) on 10.2%, with smaller clusters touching device structure, packaging, imaging and AI-assisted checking. Because records can carry multiple classes, these shares add up to more than 100% and should be read as overlap, not as a single pie chart.
The United States leads by a wide margin with 446 filings, followed by China at 109, Japan at 61, WIPO PCT filings at 59 and the European Patent Office at 31. This distribution suggests most applicants still choose the US as their first or primary filing venue for DRC-related inventions, with China representing the largest secondary market. Applicants targeting freedom-to-operate work should prioritise US prior art first, then check China and PCT filings for regional variants.
US6470489B1, titled 'Design rule checking system and method' and cited 528 times, is the most-cited record in this dataset and functions as a foundational reference that later filers had to cite or design around. High citation counts inside a searched corpus tend to favour older filings simply because they have had more time to accumulate citations, so this is a signal of historical influence rather than of current commercial dominance. Anyone drafting a new DRC claim should still review its scope, since core verification logic claims from this era remain part of the active prior art landscape.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.