Hardware Formal Verification Patents: Leaders & White Space 2026
A patent landscape review of hardware formal verification in EDA and chip design: filing trends since 2015, the leading assignees, cited prior art, and where claim space remains open, based on 45 records in scope.
Filing growth = 2021 (5 records) → 2024 (1); 2024 is the last year we treat as complete.
What hardware formal verification patents cover
Hardware formal verification patents claim methods and systems for proving that an integrated circuit design behaves according to specification, using mathematical techniques rather than simulation alone. The search scope captures records combining formal or hardware-formal verification/validation language with logic synthesis, netlist, integrated circuit design or electronic design automation terms in the claims — a deliberately narrow slice of the broader EDA patent space. The dataset in scope covers 45 published records filed or published between 2015 and the August 2026 cut-off. Because publication trails filing by roughly 18 months, the most recent one to two years understate true filing activity.
Records concentrate almost entirely under IPC class G06F, consistent with a field built on data-processing and design-automation claim language rather than measurement hardware or transmission protocols. Receiving-office data shows filings weighted toward the United States, with a secondary route through WIPO's PCT system and a smaller presence at the EPO, China and India.
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Filing trend and technology composition
The figures below are drawn directly from the 45 records in scope and the 26-company assignee ranking; no share below is computed beyond what the evidence provides.
A sharp rise and fall around a single peak year
Filings were flat at zero through 2017, built toward a peak of 5 records in 2021, then fell to 1 by 2024 — an 80% decline over that three-year span. Treat 2025 and 2026 as incomplete rather than as a continuation of that decline, since publication lag has not caught up with recent filings.
Publication lags filing by roughly 18 months, so 2025 onwards are still filling in. Growth rates on this page therefore end at 2024; running them to the last bar would understate the field.
Composition dominated by one IPC subclass
G06F covers 100% of the 45 records in scope, meaning essentially every filing in this dataset touches electric digital data processing claim language. G01R, G06N and H04L each appear in only 2.2% of records (1 of 45), marking measurement, AI-model and digital-transmission crossovers as marginal rather than mainstream in this corpus.
Shares are the percentage of the 45 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
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Try EurekaMost-cited prior art and a representative filing
Integrated circuit design model splitting for formal verification
The filing describes an apparatus that extracts netlist parameters — including node connection and execution-cycle information — from a static netlist, then analyses each node in a cycle to determine whether it is a potential split node whose projected sub-proof execution time falls under a set time limit. A split-chain module then determines whether a valid split chain exists across those candidate nodes.Filed by International Business Machines Corporation, published 2020-01-16 as US20200019652A1.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20130019216A1 | Integration of data mining and static analysis for hardware design verification | 96 |
| 2 | US9021409B2 | Integration of data mining and static analysis for hardware design verification | 43 |
| 3 | US20070226664A1 | Method and system for verifying the equivalence of digital circuits | 28 |
| 4 | US20100070940A1 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data | 22 |
| 5 | US20080301601A1 | Techniques for use with automated circuit design and simulations | 22 |
| 6 | US20110093825A1 | Techniques for analysis of logic designs with transient logic | 20 |
| 7 | US8127261B2 | System for quickly specifying formal verification environments | 19 |
| 8 | US9934342B1 | Clock gating verification during RTL stage of integrated circuit design | 18 |
| 9 | US20100185992A1 | System for Quickly Specifying Formal Verification Environments | 15 |
| 10 | US6848084B1 | Method and apparatus for verification of memories at multiple abstraction levels | 14 |
Citation counts favour older records simply by virtue of time in the corpus; read them as a signal of influence on later filings, not as a ranking of current commercial relevance.
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Browse MCP servers →What the ranking and citations indicate
Three patterns stand out once the assignee ranking, citation counts and co-filing pairs are read together.
One filer dominates a long tail
The leading assignee holds 18 records against a field of 26 ranked companies, while fifth place holds only 3 and tenth place just 2. That gap suggests a single incumbent has built a deep claim position while the remaining filers each hold a handful of records.
Filing activity fell 80% from its peak
2021 was the peak year in this dataset at 5 records; by 2024, the last year treatable as complete, filings had dropped to 1 — an 80% decline. Readers should not extend that decline into 2025-2026 given publication lag.
Named inventors, not just corporate teams, recur together
Several of the strongest co-assignee pairs in this dataset are individual names rather than corporate entities, each sharing 4 records with the same collaborator across multiple pairings. That points to a small group of named inventors filing repeatedly together outside a single large-company umbrella.
Nearly all activity sits in one IPC subclass
Every record in scope touches G06F, while G01R, G06N and H04L each appear in only a single record. That leaves measurement-integrated, AI-assisted and communications-layer formal verification claims almost entirely unclaimed within this search scope.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to eda & chip design: hardware formal verification patent landscape, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| NG CHUN KIT | MCELVAIN KENNETH S | 4 |
| NG CHUN KIT | MAIXNER RICHARD C | 4 |
| NG CHUN KIT | LAROUCHE MARIO | 4 |
| MCELVAIN KENNETH S | MAIXNER RICHARD C | 4 |
| MCELVAIN KENNETH S | LAROUCHE MARIO | 4 |
| MAIXNER RICHARD C | LAROUCHE MARIO | 4 |
| Synopsys, Inc. | NG CHUN KIT | 3 |
| Synopsys, Inc. | MCELVAIN KENNETH S | 3 |
10 co-assignee pairs were identified in this dataset, with the strongest pairs sharing 4 records each — evidence of a tight collaborative core rather than broad industry-wide co-filing.
Where to take this analysis
The dataset points to a concentrated leader, a fast-rising-then-falling filing curve, and claim space almost entirely confined to one IPC subclass. The following angles extend that reading into decisions about where to file and where to watch.
Map the white space in adjacent IPC classes
G01R, G06N and H04L each carry only one record in this scope, despite clear technical overlap with formal verification workflows — AI-assisted proof search and measurement-integrated verification are plausible extensions with almost no claim density yet.
Explore white space in EurekaWatch the leading assignee's recent filings
With 18 of the ranked records, the leading assignee's claim scope sets the boundary that new entrants have to design around; tracking its most recent publications is the fastest way to see where that boundary is moving.
Track assignee activity in EurekaRe-run the trend once 2025-2026 data settles
Publication lag means the apparent 2021-2024 decline is the last reliable read; revisiting the trend in a future cut will show whether filing activity is actually recovering or genuinely tapering off.
Set up a monitoring search in EurekaCommon questions about this landscape
This landscape was built from a search combining hardware formal verification/validation language with logic synthesis, netlist, integrated circuit design or electronic design automation terms found in the claims text. That means a record has to link formal verification specifically to hardware or IC design claim language, not just mention formal methods generally. The scope returned 45 published records between 2015 and the August 2026 cut-off, which is a narrow slice of the wider EDA patent space rather than a count of every EDA filing.
The assignee ranking covers 26 companies and named inventors, with the leader holding 18 records — a wide margin over fifth place at 3 and tenth place at 2. That pattern is a steep drop-off from one dominant filer to a long tail of smaller players, rather than a broad competitive middle. It is worth noting the ranking also includes individual named inventors alongside corporate assignees, some of whom recur as strong co-filing pairs.
Filings peaked at 5 records in 2021 and fell to 1 by 2024, an 80% decline over that span — the last three-year window that can be read as complete given publication lag. Readers should not treat 2025 and 2026 figures as confirming a continued decline, since patents published in those years are still filling in. A fair reading is that the field passed a filing peak around 2021 and has cooled since, with the most recent trend genuinely uncertain.
Essentially all 45 records in scope carry the IPC subclass G06F, covering electric digital data processing, which reflects the field's grounding in design-automation and data-processing claim language. G01R (electric and magnetic measurement), G06N (AI-based computing) and H04L (digital information transmission) each appear in only one record apiece. That leaves measurement-integrated and AI-assisted formal verification as areas with very little claimed prior art within this search scope.
The most-cited record in this dataset is a filing on integration of data mining and static analysis for hardware design verification, cited 96 times, with a related family member cited 43 times. A patent on verifying the equivalence of digital circuits and others on EDA coverage-log merging and automated circuit design simulation round out the most-cited set, each in the low-to-mid twenties of citations. High citation counts favour older records simply because they have had more time in the corpus, so they signal influence on later filings rather than current commercial weight.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.