EDA & Chip Design Patents: Who Leads, Where the Gaps Are 2026
- 45.4% of everything filed sits with just five assignees out of the 18,397 records in scope, so the core claim territory is already crowded before you look at anyone else.
- Filing volume grew 10% from 768 records in 2021 to 846 in 2024 — the last year the dataset treats as complete, since publication lags filing by about 18 months.
- G06F dominates at 70.2% of records, while narrower classes like G01R and H10W each sit near 4.6%, marking the areas still open for a first mover.
Filing growth compares 2021 (768 records) with 2024 (846) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 18,397 records in scope (CR5), not by the ranked leaders only.
What the EDA and chip design patent record actually shows
Electronic design automation and chip design patenting spans the software that synthesizes logic, checks timing and verifies layout, and the physical transistor structures those tools describe. The search string behind this dataset pairs design-automation terms — logic synthesis, timing analysis, design rule check, layout verification — with the underlying hardware they act on, which is why the technology composition leans so heavily toward G06F data processing classes even in a semiconductor-adjacent field.
18,397 records published between 2015 and the 2026 data cut give a workable picture of where claim density sits and where it doesn't. Family-level counting in the assignee ranking neutralises continuation filings and multi-jurisdiction duplicates, so the concentration figures below reflect distinct inventions rather than paperwork volume.
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Filing trend and technology composition
Two views of the same 18,397 records: how filing activity has moved year over year, and which IPC subclasses carry the claim volume today.
Filing trend, 2017-2026
Recorded filings ran from 758 in 2017 to a peak of 855 in 2023. The 2021-to-2024 span shows +10% growth (768 to 846) — the clearest complete-year read available, since 2025 and 2026 are still filling in under publication lag and should not be read as a slowdown.
IPC subclass distribution
G06F carries 70.2% of records, consistent with the search string's emphasis on automation logic; H01L and H10D (24.6% and 9.5%) cover the semiconductor-device side. Smaller subclasses — G01R, H10W, H03K, G11C and H10P, each in the 3.7%-4.6% range — mark narrower, less contested claim territory. Shares add to more than 100% because a single record can carry several IPC classes.
Shares are the percentage of the 18,397 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on EDA & Chip Design Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about eda & chip design patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative filing and the most-cited prior art
US5727187A — Method of using logical names in post-synthesis electronic design automation systems
A method used by an electronic design automation system for allowing the use of logical names from a register transfer level description of an integrated circuit design in timing notes and simulation tests written for timing analysis and simulation programs. A synthesis program generates a state map file containing an entry for the logical name for each state defined in the register transfer level description of the integrated circuit. The gate level name generated by the synthesis program corresponding to the logical state name is stored in the entry, providing a one-to-one mapping between logical state names and gate-level state names.Filed by Unisys Corporation; granted 1998-03-10. The mapping technique it describes — tying human-readable logical names through to gate-level names for timing and simulation — sits upstream of most modern synthesis-to-verification flows.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6534395B2 | Method of forming graded thin films using alternating pulses of vapor phase reactants | 1,323 |
| 2 | US20010041250A1 | Graded thin films | 985 |
| 3 | US20020115252A1 | Dielectric interface films and methods therefor | 804 |
| 4 | US20050023656A1 | Vertical system integration | 785 |
| 5 | US6209123B1 | Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transis… | 632 |
| 6 | US20050181555A1 | Thin films | 622 |
| 7 | US6509217B1 | Inexpensive, reliable, planar RFID tag structure and method for making same | 582 |
| 8 | US6470489B1 | Design rule checking system and method | 528 |
| 9 | US20050251771A1 | Integrated circuit layout design methodology with process variation bands | 508 |
| 10 | US6370679B1 | Data hierarchy layout correction and verification method and apparatus | 502 |
Citation counts favor older filings simply because they have had more time to be cited within this corpus; treat them as a signal of influence on the field, not of current filing activity.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns recur across the assignee ranking, the filing trend and the class breakdown — each has a direct bearing on where a new filing is likely to land clean.
The top of the field is genuinely crowded
Five assignees hold 8,361 of the 18,397 records in scope, and the top ten extend that to 63.6% (11,693 records). That is concentration at the very top of the ranking, not an even spread across the 100 ranked companies — a new entrant filing in the same core synthesis and timing-analysis claims is filing directly against that density.
Filing activity is still rising, not cooling
The complete-year data runs through 2024, where volume sits above both 2021 and the earlier-decade baseline, with 2023 the peak year recorded so far at 855. The apparent drop into 2025-2026 is a publication-lag artefact — those years are still being filled in and should not be read as declining interest.
Software-side claims dominate the class mix
G06F digital data processing appears on 70.2% of records, well ahead of the hardware-side H01L (24.6%) and H10D (9.5%). Because records carry multiple classes, this says claim space is occupied in the automation-logic layer specifically, not that the whole field is saturated — the narrower classes below 5% look comparatively open.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to eda & chip design patent landscape, with the prior art for and against each one.
Who holds the ground, and where momentum has cooled
The ranked leaders account for most of the volume, but the latest-year momentum figures show even the largest filers pulling back sharply from their own recent pace — a pattern worth separating from long-run share.
One filer sits well ahead of the field
The leading assignee's 3,502 records dwarf the fifth-place figure of 1,120 and the tenth-place figure of 359, which is the steep drop-off typical of a field anchored by a handful of large EDA and foundry players rather than a flat distribution.
Recent-year filing counts have dropped sharply across the board
Several of the largest assignees show latest-year filing counts far below their prior year — declines in the -88% to -100% range are consistent across multiple leaders. This should be read alongside the 18-month publication lag rather than as a sudden retreat from the field; the complete-year trend through 2024 still shows growth.
Co-filing is concentrated within corporate families
The strongest co-assignee pairs link a parent company to its own regional IP or subsidiary entities rather than to external partners, suggesting most joint filings in this dataset reflect internal corporate structure rather than cross-company collaboration.
| Assignee | Recent year | YoY |
|---|---|---|
| ARM Ltd | 17 | -88% |
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 5 | -91% |
| Intel Corporation | 2 | -88% |
| International Business Machines Corporation (IBM) | 0 | -100% |
| Synopsys, Inc. | 0 | -100% |
| Cadence Design Systems, Inc. | 0 | — |
| Altera Corporation | 0 | -100% |
| LSI Corporation | 0 | — |
Where to take this next
The dataset points to specific follow-up questions rather than a single conclusion — each depends on what the reader is trying to decide.
Check freedom-to-operate against the top filers
With 45.4% of records held by five assignees, a freedom-to-operate review for any core synthesis, timing-analysis or layout-verification claim should start with those portfolios before looking further down the ranking.
Run a freedom-to-operate check in EurekaWatch the under-5%-share classes for openings
G01R, H10W, H03K, G11C and H10P each sit near or below 4.6% of records — narrow enough that a well-drafted claim may still find clear space, particularly at the measurement and memory-verification boundary.
Explore white space in EurekaRe-run the trend once 2025-2026 fills in
Because publication lags filing by roughly 18 months, the apparent drop-off after 2024 is not yet reliable evidence of a slowdown; revisit the filing trend once those years mature before drawing conclusions about momentum.
Track filing trends in EurekaCommon questions about EDA and chip design patents
The assignee ranking behind this dataset is led by one company with 3,502 records, well ahead of the field, with the fifth-ranked assignee at 1,120 and the tenth at 359. Together the top five hold 45.4% of all 18,397 records in scope, and the top ten hold 63.6%. That drop-off from first to tenth place is steep rather than gradual, which is typical of a field anchored by a small number of large EDA software vendors and foundries rather than spread evenly across many mid-sized filers.
Yes, based on the most recent complete years: filings rose from 768 records in 2021 to 846 in 2024, a 10% increase, with 2023 the highest single year recorded at 855. Filing counts in 2025 and 2026 appear lower in the raw data, but that reflects the roughly 18-month lag between filing a patent and its publication, not an actual decline. Any conclusion about a slowdown drawn from the two most recent years alone would be premature.
G06F, the digital data processing class, appears on 70.2% of the 18,397 records in scope, reflecting the heavy weighting toward design-automation software logic — synthesis, timing analysis, verification — built into the search criteria. The semiconductor-device classes H01L and H10D follow at 24.6% and 9.5% respectively. Narrower subclasses including G01R, H10W, H03K, G11C and H10P each sit in the 3.7%-4.6% range, marking areas of comparatively lower claim density.
The subclasses furthest from the dominant G06F share are the most promising starting point: G01R (electric and magnetic measurement), H10W and H10P (semiconductor device variants), H03K (pulse technique and logic circuits) and G11C (static and digital memories) each account for under 5% of records. Combined with the fact that concentration is heaviest in the top five to ten assignees rather than spread across the full ranking, a new claim drafted around a specific measurement or verification technique in one of these narrower classes is less likely to run into dense prior art than a general synthesis or timing-analysis claim.
Several of the most active assignees show year-over-year declines in the -88% to -100% range in the latest year of data, but this is a publication-lag effect rather than a genuine drop in filing activity. Patent applications typically publish about 18 months after filing, so the most recent one to two years in any dataset are structurally incomplete. The reliable complete-year trend, which runs through 2024, still shows overall growth of 10% from 2021, so the latest-year numbers should be read as provisional rather than as evidence of retreat.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.