Power Integrity Simulation Patents: Leaders, Trends & Gaps 2026
Filing growth compares 2021 (2 records) with 2024 (2) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
A narrow, method-heavy filing field
Power integrity simulation sits at the boundary between chip design tooling and physical verification: patent claims here describe how engineers model, measure and correct voltage noise and power delivery issues on and around a semiconductor die before it is manufactured. The scope defined by this dataset is small — 14 published records — but the composition is telling: the overwhelming majority of claims fall under G06F, the digital-data-processing class, meaning the field is dominated by simulation methods and software workflows rather than new physical structures.
Filing has been flat rather than growing across the only complete comparison window the data supports, and the assignee field is fragmented across 11 ranked companies with no single filer holding a commanding position. That combination — small record count, method-heavy claims, fragmented ownership — points to a field still being actively defined at the claim level rather than one already settled by an incumbent.
Filing trend and technology composition
The 14 records in scope span 2015 through the partial 2026 year, with technology claims concentrated in a small number of IPC subclasses.
Filing activity, 2017-2026
Filings peaked at 4 in 2018. The three-year comparison the dataset supports, 2021 (2) against 2024 (2), shows flat filing volume — 0% growth — over that span. Because publication trails filing by roughly 18 months, 2025 and 2026 figures are still incomplete and should not be read as a decline.
Where the claims sit
G06F digital-data-processing claims appear in 85.7% of the 14 records, confirming that most activity is simulation-method work rather than new device structures. H01L semiconductor-device claims (28.6%) and G05F variable-control claims (21.4%) form the next tier, with G01R, G11C and H04B each present in only one record (7.1%).
Shares are the percentage of the 14 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on EDA & Chip Design: Power Integrity Simulation Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about eda & chip design: power integrity simulation patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited and most representative filings
KR1020110099966A — Apparatus for generating current source in integrated circuit electromagnetic model and the method
Filed by Samsung Electronics on 2011-09-09, this filing describes a method for generating a current source within an Integrated Circuit Electromagnetic Model (ICEM) — the power-source model used for power integrity and EMI simulation of semiconductor ICs. The method is built to apply varied input data patterns, including patterns carrying skew between them, so that PI/EMI simulation can proceed efficiently across different design cases.Abstract text is drawn directly from the filing as published.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | CN109508505A | 一种印刷电路板电源完整性的仿真方法 | 19 |
| 2 | US20200134116A1 | Simulation system and method | 8 |
| 3 | US10599798B1 | Double glitch capture mode power integrity analysis | 6 |
| 4 | CN107644122A | 一种ODB++文件修改方法、装置及可读存储介质 | 6 |
| 5 | US20190370425A1 | On-die decoupling capacitor area optimization | 4 |
| 6 | US20210327801A1 | Platform power integrity design including package standard power integrity model and compact voltage regulato… | 3 |
| 7 | KR1020110099966A | Apparatus for generating current source in integrated circuit electromagnetic model and the method | 3 |
| 8 | US20200184135A1 | Double glitch capture mode power integrity analysis | 1 |
Ranked by citation count within the 14 records in scope; older filings tend to lead simply by having had more time to be cited.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Publication numbers are shown where the record carries one (8 of 8 rows); clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers actually indicate
Three findings stand out once the record counts, citation data and filing timeline are read together.
Volume is flat, not declining
The dataset's only valid complete-year comparison shows 2 filings in 2021 and 2 in 2024. The apparent drop-off after 2024 is a publication-lag artefact, not a real decline, since publication trails filing by roughly 18 months.
Claims cluster on method, not structure
Digital-data-processing claims dominate the record set, well ahead of the H01L device class (28.6%) and G05F control class (21.4%). Most competitive activity is on simulation workflow, not new physical hardware.
No single gatekeeper
The leader holds 3 filings; the field drops quickly to single-filing entrants by fifth place and beyond. This is a fragmented landscape rather than one controlled by a dominant incumbent.
Older simulation-method filings carry the most influence
CN109508505A leads the citation count at 19, followed by US20200134116A1 at 8. Both are simulation-method filings, suggesting the field's most referenced claim territory is computational rather than physical.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to eda & chip design: power integrity simulation patent landscape, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| YANG YIHONG | WANG LONG | 2 |
| YANG YIHONG | THOTA SRINIVAS | 2 |
| YANG YIHONG | SAM SU MI | 2 |
| YANG YIHONG | QIAN WEI | 2 |
| YANG YIHONG | CHEN JUE | 2 |
| YANG YIHONG | CHEN CHUNG HAO JOSEPH | 2 |
| YANG YIHONG | CHEN CHI TE | 2 |
| YANG YIHONG | CAI XING JIAN | 2 |
Co-assignee pairing in this dataset is limited to 10 pairs, with the strongest recurring pairing appearing twice across different collaborators — a modest but real signal of shared inventorship rather than purely single-assignee filing.
Where to take this analysis
This landscape flags the shape of the field; the next steps depend on whether the goal is clearance, monitoring, or filing strategy.
Verify freedom to operate on simulation methods
Since most claims cluster on G06F simulation workflows rather than device structures, a clearance search should focus on method claims first, particularly around the highest-cited filings.
Run a clearance search in EurekaTrack the fragmented assignee field
With 11 companies in the ranking and no dominant leader, new entrants and shifts in filing activity are easy to miss without ongoing monitoring.
Set up assignee tracking in EurekaTest claim language in the under-claimed branches
G01R, G11C and H04B each appear in only one of the 14 records, leaving room to test claim scope before the space fills in.
Draft and check claims in EurekaCommon questions on this landscape
The assignee ranking for this dataset covers 11 companies, led by a filer with 3 records ahead of a long tail that includes entrants with a single filing each, down to the tenth-ranked company at 1. Names in the ranking span EDA and simulation software vendors, large semiconductor manufacturers, and a few printed-circuit-board specialists, which reflects how power integrity simulation sits at the intersection of chip design tooling and physical layout verification. No single company holds a dominant share of the 14 total records, so this is not a field with one clear gatekeeper.
G06F, the digital-data-processing class, appears in 85.7% of the 14 records in scope, meaning most claims describe computational simulation methods rather than new hardware. H01L semiconductor-device claims and G05F control-circuit claims are the next largest groups, at 28.6% and 21.4% of records respectively. This pattern suggests that most patent activity is defending simulation algorithms and workflows, with device-level claims filed as a secondary layer alongside them.
Using the only complete-year comparison available, filings held flat at 2021 (2) versus 2024 (2) — 0% change over that three-year span. The peak year on record so far is 2018, at 4 filings. Because publication typically lags actual filing by around 18 months, the lower counts shown for 2025 and 2026 are an artefact of that reporting delay, not evidence of a slowdown, and should not be read as a trend.
Of the receiving offices recorded in this dataset, the United States accounts for 10, China for 3, and South Korea for 1. That distribution points to the US as the primary jurisdiction for contesting claims in this field, with China as a secondary but active filing location. Teams evaluating freedom to operate should weight their search and clearance work toward US-filed claims first, then extend to Chinese filings.
KR1020110099966A, filed by Samsung Electronics in 2011, claims a method for generating a current source within an Integrated Circuit Electromagnetic Model used for power integrity and EMI simulation of semiconductor ICs. Its distinguishing feature is applying varied and skewed input-data patterns directly within the current-source generation step, rather than treating pattern variation as a separate simulation input. It matters because it predates most of the other 13 records in this dataset and sits close to a foundational method for ICEM-based power-source modelling that later filers have had to design around.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.